Tampere University of Technology

TUTCRIS Research Portal

Jani Boutellier

  1. Published

    Actor Merging for Dataflow Process Networks

    Boutellier, J., Ersfolk, J., Lilius, J., Mattavelli, M., Roquier, G. & Silvén, O., 15 May 2015, In : IEEE Transactions on Signal Processing. 63, 10, p. 2496-2508 13 p., 7055878.

    Research output: Contribution to journalArticleScientificpeer-review

  2. Published

    A methodology for profiling and partitioning stream programs on many-core architectures

    Michalska, M., Boutellier, J. & Mattavelli, M., 2015, Procedia Computer Science. Vol. 51. p. 2962-2966 5 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  3. Published

    Application-specific instruction processor for extracting local binary patterns

    Boutellier, J., Lundbom, I., Janhunen, J., Ylimainen, J. & Hannuksela, J., 2012, DASIP 2012 - Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing. p. 82-89 8 p. 6385363

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  4. Published

    Applying the adaptive hybrid flow-Shop scheduling method to schedule a 3GPP LTE physical layer algorithm onto many-core digital signal processors

    Heulot, J., Boutellier, J., Pelcat, M., Nezan, J. F. & Aridhi, S., 2013, Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2013. p. 123-129 7 p. 6604235

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  5. Published

    Automated design of networks of transport-triggered architecture processors using dynamic dataflow programs

    Yviquel, H., Boutellier, J., Raulet, M. & Casseau, E., Nov 2013, In : Signal Processing: Image Communication. 28, 10, p. 1295-1302 8 p.

    Research output: Contribution to journalArticleScientificpeer-review

  6. Published

    Automatic hierarchical discovery of quasi-static schedules of RVC-CAL dataflow programs

    Boutellier, J., Raulet, M. & Silvén, O., 2013, In : Journal of Signal Processing Systems. 71, 1, p. 35-40 6 p.

    Research output: Contribution to journalArticleScientificpeer-review

  7. Published

    Automatic synthesis of TTA processor networks from RVC-CAL dataflow programs

    Boutellier, J., Silvén, O. & Raulet, M., 2011, 2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings. p. 25-30 6 p. 6088944

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  8. Published

    Binarized Convolutional Neural Networks for Efficient Inference on GPUs

    Khan, M., Huttunen, H. & Boutellier, J., Sep 2018, 2018 26th European Signal Processing Conference (EUSIPCO). IEEE, p. 682-686

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  9. Published

    BM3D image denoising using heterogeneous computing platforms

    Sarjanoja, S., Boutellier, J. & Hannuksela, J., 28 Dec 2015, DASIP 2015 - Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing. IEEE COMPUTER SOCIETY PRESS, Vol. 2015-December. 7367257

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  10. Published

    Comparing Optimization Methods of Neural Networks for Real-time Inference

    Khan, M., Lunnikivi, H., Huttunen, H. & Boutellier, J., 3 Sep 2019, 2019 27th European Signal Processing Conference (EUSIPCO). IEEE, 5 p. (European Signal Processing Conference).

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

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