Jarno Vanne
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End-to-End Real-Time ROI-Based Encryption in HEVC Videos
Abu Taha, M., Sidaty, N., Hamidouche, W., Déforges, O., Vanne, J. & Viitanen, M., Sep 2018, 2018 European Signal Processing Conference (EUSIPCO). IEEE, p. 171-174Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
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Block-level parallel processing for scaling evenly divisible images
Aho, E., Vanne, J., Hämäläinen, T. D. & Kuusilinna, K., 2005, In : IEEE Transactions on Circuits and Systems. Part 1: Regular Papers. 52, 12, p. 2717-2725Research output: Contribution to journal › Article › Scientific › peer-review
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Xor-scheme Implementations In Configurable Pararell Memory
Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T., 2002, WSOC Proceedings of the International Workshop on System on Chip for Real-time Applications, July 5 - 7, 2002, Banff, Canada. p. 287-298Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific
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Address computation in configurable parallel memory architecture
Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T. D., 2004, In : IEICE Transactions on Information and Systems. E87-D, 7, p. 1674-1681Research output: Contribution to journal › Article › Scientific › peer-review
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Parallel memory implementation for arbitrary stride accesses
Aho, E., Vanne, J. & Hämäläinen, T. D., 2006, Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 17-20 July, 2006, Samos, Greece. p. 1-6 6 p.Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
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Configurable implementation of parallel memory based real-time video downscaler
Aho, E., Vanne, J., Hämäläinen, T. D. & Kuusilinna, K., 2007, In : Microprocessors and Microsystems. 31, 5, p. 283-292Research output: Contribution to journal › Article › Scientific › peer-review
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Diamond Scheme Implementations in Configurable Parallel Memory
Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T., 2002, Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems, April 17-19, 2002, Brno, Czech Republic. Straube, B. (ed.). p. 211-218Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific
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Block-level parallel processing for scaling evenly divisible frames
Aho, E., Vanne, J., Hämäläinen, T. D. & Kuusilinna, K., 2005, Proceedings of ISCAS 2005 IEEE International Symposium on Circuits and Systems, 23-26 May 2005, Kobe, Japan. p. 1134-1137Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
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Access Format Implementations in Configurable Parallel Memory
Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T., 2002, Proceedings of ICIS 2002 the 2nd International Conference on Computer and Information Science, August 8-9, 2002, Seoul, Korea. Yang, H. S. (ed.). p. 59-64Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
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Parallel memory architecture for arbitrary stride accesses
Aho, E., Vanne, J. & Hämäläinen, T. D., 2006, Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 18-21 April, 2006, Prague, Czech Republic. Reorda, M. S. (ed.). p. 65-70Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
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