Tampere University of Technology

TUTCRIS Research Portal

Jarno Vanne

  1. Article › Scientific › Peer-reviewed
  2. Published

    A configurable motion estimation architecture for block-matching algorithms

    Vanne, J., Aho, E., Kuusilinna, K. & Hämäläinen, T. D., 2009, In : IEEE Transactions on Circuits and Systems for Video Technology. 19, 4, p. 466-476

    Research output: Contribution to journalArticleScientificpeer-review

  3. Published

    Address computation in configurable parallel memory architecture

    Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T. D., 2004, In : IEICE Transactions on Information and Systems. E87-D, 7, p. 1674-1681

    Research output: Contribution to journalArticleScientificpeer-review

  4. Published

    A high-performance sum of absolute difference implementation for motion estimation

    Vanne, J., Aho, E., Hämäläinen, T. D. & Kuusilinna, K., 2006, In : IEEE Transactions on Circuits and Systems for Video Technology. 16, 7, p. 876-883

    Research output: Contribution to journalArticleScientificpeer-review

  5. Published

    A parallel memory system for variable block-size motion estimation algorithms

    Vanne, J., Aho, E., Hämäläinen, T. D. & Kuusilinna, K., 2008, In : IEEE Transactions on Circuits and Systems for Video Technology. 18, 4, p. 538-543

    Research output: Contribution to journalArticleScientificpeer-review

  6. Published

    Are We There Yet? A Study on the State of High-level Synthesis

    Lahti, S., Sjövall, P., Vanne, J. & Hämäläinen, T. D., May 2019, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38, 5, p. 898-911

    Research output: Contribution to journalArticleScientificpeer-review

  7. Published

    Block-level parallel processing for scaling evenly divisible images

    Aho, E., Vanne, J., Hämäläinen, T. D. & Kuusilinna, K., 2005, In : IEEE Transactions on Circuits and Systems. Part 1: Regular Papers. 52, 12, p. 2717-2725

    Research output: Contribution to journalArticleScientificpeer-review

  8. Published

    Comments on "Winscale: An image-scaling algorithm using an area pixel model"

    Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T. D., 2005, In : IEEE Transactions on Circuits and Systems for Video Technology. 15, 3, p. 454-455

    Research output: Contribution to journalArticleScientificpeer-review

  9. Published

    Comparative Rate-Distortion-Complexity Analysis of HEVC and AVC Video Codecs

    Vanne, J., Viitanen, M., Hämäläinen, T. D. & Hallapuro, A., 2012, In : IEEE Transactions on Circuits and Systems for Video Technology. 22, 12, p. 1885-1898

    Research output: Contribution to journalArticleScientificpeer-review

  10. Published

    Configurable data memory for multimedia processing

    Aho, E., Vanne, J. & Hämäläinen, T. D., 2008, In : Journal of Signal Processing Systems. 50, 2, p. 231-249

    Research output: Contribution to journalArticleScientificpeer-review

  11. Configurable implementation of parallel memory based real-time video downscaler

    Aho, E., Vanne, J., Hämäläinen, T. D. & Kuusilinna, K., 2007, In : Microprocessors and Microsystems. 31, 5, p. 283-292

    Research output: Contribution to journalArticleScientificpeer-review

  12. Published

    Efficient Mode Decision Schemes for HEVC Inter Prediction

    Vanne, J., Viitanen, M. & Hämäläinen, T. D., 2014, In : IEEE Transactions on Circuits and Systems for Video Technology. 24, 9, p. 1579-1593 15 p.

    Research output: Contribution to journalArticleScientificpeer-review

  13. Published

    Generic Software Framework for a Line-Buffer-Based Image Processing Pipeline

    Määttä, J-M., Vanne, J., Hämäläinen, T. D. & Nikkanen, J., 2011, In : IEEE Transactions on Consumer Electronics. 57, 3, p. 1442-1449

    Research output: Contribution to journalArticleScientificpeer-review

  14. Chapter › Scientific › Peer-reviewed
  15. Published

    Configurable Address Computation in a Parallel Memory Architecture

    Aho, E., Vanne, J., Kuusilinna, K., Hämäläinen, T. & Saarinen, J., 2001, Advances in Signal Processing and Computer Technologies. Electrical and Computer Engineering Series. A Series of Reference Books and Textbooks.. Antoniou, G. (ed.). Kreikka: WSES Press, p. 390-395

    Research output: Chapter in Book/Report/Conference proceedingChapterScientificpeer-review

  16. Published

    Configurable Parallel Memory Implementation For System-on-Chip Designs

    Vanne, J., Aho, E., Kuusilinna, K. & Hämäläinen, T., 2003, System-on-Chip for Real-Time Applications. Badawy, W. & Jullien, G. A. (eds.). Kluwer Academic Publish ers, p. 237-248

    Research output: Chapter in Book/Report/Conference proceedingChapterScientificpeer-review

  17. Published

    XOR-scheme Implementations In Configurable Parallel Memory

    Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T., 2002, System-on-Chip for Real-Time Applications. Badawy, W. & Jullien, G. A. (eds.). Kluwer Academic Publish ers, p. 249-261 (The International Series in Engineering and Computer Science).

    Research output: Chapter in Book/Report/Conference proceedingChapterScientificpeer-review

  18. Conference contribution › Scientific › Not peer-reviewed
  19. Published

    Configurable Address Computation in a Parallel Memory Architecture

    Aho, E., Vanne, J., Kuusilinna, K., Hämäläinen, T. & Saarinen, J., 2001, Proceedings of the 5th WSES International Conference on Circuits, Systems, Communications and Computers (CSCC 2001), July 8-15, 2001, Rethymno, Greece. Mastorakis, N. (ed.). p. 4941-4946

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  20. Published

    Configurable Paralell Memory Implementation For Systenm-on-Chip Designs

    Vanne, J., Aho, E., Kuusilinna, K. & Hämäläinen, T., 2002, WSOC Proceedings of the International Workshop on System on Chip for Real-time Applications, July 5 - 7, 2002, Banff, Canada. p. 253-264

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  21. Published

    Co-simulation of Configurable Parallel Memory Architecture and Processor

    Vanne, J., Aho, E., Kuusilinna, K. & Hämäläinen, T., 2002, Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, April 17-19, 2002, Brno, Czech Republic. Straube, B. (ed.). p. 310-313

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  22. Published

    Diamond Scheme Implementations in Configurable Parallel Memory

    Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T., 2002, Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems, April 17-19, 2002, Brno, Czech Republic. Straube, B. (ed.). p. 211-218

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  23. Published

    Xor-scheme Implementations In Configurable Pararell Memory

    Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T., 2002, WSOC Proceedings of the International Workshop on System on Chip for Real-time Applications, July 5 - 7, 2002, Banff, Canada. p. 287-298

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

Previous 1 2 3 4 Next

ID: 66514