Tampere University of Technology

TUTCRIS Research Portal

Jarno Vanne

  1. 2007
  2. Configurable implementation of parallel memory based real-time video downscaler

    Aho, E., Vanne, J., Hämäläinen, T. D. & Kuusilinna, K., 2007, In : Microprocessors and Microsystems. 31, 5, p. 283-292

    Research output: Contribution to journalArticleScientificpeer-review

  3. Published

    Piiri ja menetelmä erojen itseisarvojen summan laskemiseksi nopeasti ja tehokkaasti. Krets och metod för att räkna en sum av absoluta skillnader snabbt och effektivt

    Vanne, J., Aho, E. & Hämäläinen, T. D., 2007, Patent No. Pat. FI 117956 B, Priority date 30 Apr 2007, Priority No. (21) 20050388

    Research output: PatentScientific

  4. 2006
  5. Published

    A high-performance sum of absolute difference implementation for motion estimation

    Vanne, J., Aho, E., Hämäläinen, T. D. & Kuusilinna, K., 2006, In : IEEE Transactions on Circuits and Systems for Video Technology. 16, 7, p. 876-883

    Research output: Contribution to journalArticleScientificpeer-review

  6. Published

    Parallel memory architecture for arbitrary stride accesses

    Aho, E., Vanne, J. & Hämäläinen, T. D., 2006, Proceedings of the 2006 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, 18-21 April, 2006, Prague, Czech Republic. Reorda, M. S. (ed.). p. 65-70

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  7. Published

    Parallel memory implementation for arbitrary stride accesses

    Aho, E., Vanne, J. & Hämäläinen, T. D., 2006, Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 17-20 July, 2006, Samos, Greece. p. 1-6 6 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  8. 2005
  9. Published

    Block-level parallel processing for scaling evenly divisible frames

    Aho, E., Vanne, J., Hämäläinen, T. D. & Kuusilinna, K., 2005, Proceedings of ISCAS 2005 IEEE International Symposium on Circuits and Systems, 23-26 May 2005, Kobe, Japan. p. 1134-1137

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  10. Published

    Block-level parallel processing for scaling evenly divisible images

    Aho, E., Vanne, J., Hämäläinen, T. D. & Kuusilinna, K., 2005, In : IEEE Transactions on Circuits and Systems. Part 1: Regular Papers. 52, 12, p. 2717-2725

    Research output: Contribution to journalArticleScientificpeer-review

  11. Published

    Comments on "Winscale: An image-scaling algorithm using an area pixel model"

    Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T. D., 2005, In : IEEE Transactions on Circuits and Systems for Video Technology. 15, 3, p. 454-455

    Research output: Contribution to journalArticleScientificpeer-review

  12. 2004
  13. Published

    Address computation in configurable parallel memory architecture

    Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T. D., 2004, In : IEICE Transactions on Information and Systems. E87-D, 7, p. 1674-1681

    Research output: Contribution to journalArticleScientificpeer-review

  14. 2003
  15. Published

    Configurable Parallel Memory Implementation For System-on-Chip Designs

    Vanne, J., Aho, E., Kuusilinna, K. & Hämäläinen, T., 2003, System-on-Chip for Real-Time Applications. Badawy, W. & Jullien, G. A. (eds.). Kluwer Academic Publish ers, p. 237-248

    Research output: Chapter in Book/Report/Conference proceedingChapterScientificpeer-review

ID: 66514