Tampere University of Technology

TUTCRIS Research Portal

Jarno Vanne

  1. 2002
  2. Published

    Access Format Implementations in Configurable Parallel Memory

    Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T., 2002, Proceedings of ICIS 2002 the 2nd International Conference on Computer and Information Science, August 8-9, 2002, Seoul, Korea. Yang, H. S. (ed.). p. 59-64

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  3. Published

    Configurable Paralell Memory Implementation For Systenm-on-Chip Designs

    Vanne, J., Aho, E., Kuusilinna, K. & Hämäläinen, T., 2002, WSOC Proceedings of the International Workshop on System on Chip for Real-time Applications, July 5 - 7, 2002, Banff, Canada. p. 253-264

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  4. Published

    Co-simulation of Configurable Parallel Memory Architecture and Processor

    Vanne, J., Aho, E., Kuusilinna, K. & Hämäläinen, T., 2002, Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop, April 17-19, 2002, Brno, Czech Republic. Straube, B. (ed.). p. 310-313

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  5. Published

    Diamond Scheme Implementations in Configurable Parallel Memory

    Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T., 2002, Proceedings of IEEE Design and Diagnostics of Electronic Circuits and Systems, April 17-19, 2002, Brno, Czech Republic. Straube, B. (ed.). p. 211-218

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  6. Published

    Enhanced Configurable Parallel Memory Architecture

    Vanne, J., Aho, E., Kuusilinna, K. & Hämäläinen, T., 2002, Proceedings of DCD 2002 Euromicro Symposium on Digital System Design; Architectures, Methods and Tools, September 4-6, 2002, Dortmund, Germany. Edwards, M. (ed.). p. 28-35

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  7. Published

    XOR-scheme Implementations In Configurable Parallel Memory

    Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T., 2002, System-on-Chip for Real-Time Applications. Badawy, W. & Jullien, G. A. (eds.). Kluwer Academic Publish ers, p. 249-261 (The International Series in Engineering and Computer Science).

    Research output: Chapter in Book/Report/Conference proceedingChapterScientificpeer-review

  8. Published

    Xor-scheme Implementations In Configurable Pararell Memory

    Aho, E., Vanne, J., Kuusilinna, K. & Hämäläinen, T., 2002, WSOC Proceedings of the International Workshop on System on Chip for Real-time Applications, July 5 - 7, 2002, Banff, Canada. p. 287-298

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

  9. 2001
  10. Published

    Configurable Address Computation in a Parallel Memory Architecture

    Aho, E., Vanne, J., Kuusilinna, K., Hämäläinen, T. & Saarinen, J., 2001, Advances in Signal Processing and Computer Technologies. Electrical and Computer Engineering Series. A Series of Reference Books and Textbooks.. Antoniou, G. (ed.). Kreikka: WSES Press, p. 390-395

    Research output: Chapter in Book/Report/Conference proceedingChapterScientificpeer-review

  11. Published

    Configurable Address Computation in a Parallel Memory Architecture

    Aho, E., Vanne, J., Kuusilinna, K., Hämäläinen, T. & Saarinen, J., 2001, Proceedings of the 5th WSES International Conference on Circuits, Systems, Communications and Computers (CSCC 2001), July 8-15, 2001, Rethymno, Greece. Mastorakis, N. (ed.). p. 4941-4946

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientific

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