Tampere University of Technology

TUTCRIS Research Portal

Pekka Jääskeläinen

Organisations

Education / Academic qualification

Master of Science (Technology), Information Technology, Tampere University of Technology
Doctor of Science (Technology), Information Technology, Tampere University of Technology

Thesis supervision, examination and instruction at TUT (since 2008)

Kalle Immonen. 2017. Real-Time Noise Removal in Foveated Path Tracing. (Examiner to master's thesis).
Matias Koskela. 2015. Software-Based Ray Tracing for Mobile Devices. (Examiner to master's thesis).
Henry Linjam�ki. 2015. Instruction Memory Hierarchy Generation for Customized Processors. (Examiner to master's thesis).
Joonas Multanen. 2015. Hardware Optimizations for Low-Power Processors. (Examiner to master's thesis).
Nirajan Pant. 2015. Discrete Sine and Cosine Transforms on Parallel Processors. (Examiner to master's thesis).
Janne Helkala. 2014. Variable Length Instruction Compression on Transport Triggered Architectures. (Examiner to master's thesis).
Mikko J�rvel�. 2014. Vector Operation Support for Transport Triggered Architectures. (Examiner to master's thesis).
Ville Korhonen. 2014. Portable OpenCL Out-of-Order Execution Framework for Heterogeneous Platforms. (Examiner to master's thesis).
Tomi �ij�. 2014. Integer Linear Programming Based Code Generation for Exposed Datapath. (Examiner to master's thesis).
Timo Viitanen. 2012. Floating-Point Arithmetic in Transport Triggered Architectures. (Examiner to master's thesis).
Otto Esko. 2011. ASIP Integration and Verification Flow for FPGA. (Examiner to master's thesis).

Grants and awards

01.08.2017 - 30.11.2017. . .

ID: 50893