Tampere University of Technology

TUTCRIS Research Portal

Timo Hämäläinen

  1. 2019
  2. Published

    Feasibility of FPGA accelerated IPsec on cloud

    Vajaranta, M., Oinonen, A., Hämäläinen, T. D., Viitamäki, V., Markunmäki, J. & Kulmala, A., 1 Nov 2019, In : Microprocessors and Microsystems. 71, 102861.

    Research output: Contribution to journalArticleScientificpeer-review

  3. Published

    Are We There Yet? A Study on the State of High-level Synthesis

    Lahti, S., Sjövall, P., Vanne, J. & Hämäläinen, T. D., May 2019, In : IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 38, 5, p. 898-911

    Research output: Contribution to journalArticleScientificpeer-review

  4. Published

    Open Framework for Error-Compensated Gaze Data Collection with Eye Tracking Glasses

    Siivonen, K., Sainio, J., Viitanen, M., Vanne, J. & Hämäläinen, T. D., 2019, Proceedings - 2018 IEEE International Symposium on Multimedia, ISM 2018. IEEE, p. 299-302 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  5. 2018
  6. Published

    Eye-Controlled Region of Interest HEVC Encoding

    Sainio, J., Ylä-Outinen, A., Viitanen, M., Vanne, J. & Hämäläinen, T. D., Dec 2018, 2018 IEEE International Symposium on Multimedia (ISM). IEEE, 2 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  7. Published

    Visualization of memory map information in embedded system design

    Teuho, M., Pekkarinen, E. & Hämäläinen, T. D., 12 Oct 2018, Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018. IEEE, p. 163-166 4 p. 8491811

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  8. Published

    Feasibility of FPGA accelerated IPsec on cloud

    Vajaranta, M., Viitamäki, V., Oinonen, A., Hämäläinen, T. D., Kulmala, A. & Markunmäki, J., 31 Aug 2018, 2018 Euromicro Conference on Digital System Design (DSD). IEEE

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  9. Published

    Modeling RISC-V processor in IP- XACT

    Pekkarinen, E. & Hämäläinen, T. D., 31 Aug 2018, Proceedings - 21st Euromicro Conference on Digital System Design, DSD 2018. IEEE, p. 140-147

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  10. Published

    Low latency edge rendering scheme for interactive 360 degree virtual reality gaming

    Viitanen, M., Vanne, J., Hämäläinen, T. D. & Kulmala, A., 19 Jul 2018, Proceedings - 2018 IEEE 38th International Conference on Distributed Computing Systems, ICDCS 2018. IEEE, p. 1557-1560 4 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  11. Published

    Rate-distortion-complexity optimized coding scheme for kvazaar HEVC intra encoder

    Lemmetti, A., Kallio, E., Viitanen, M., Vanne, J. & Hamalainen, T. D., 19 Jul 2018, Proceedings - DCC 2018: 2018 Data Compression Conference. IEEE, 1 p.

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

  12. Published

    FPGA-Powered 4K120p HEVC Intra Encoder

    Sjövall, P., Viitamäki, V., Vanne, J., Hämäläinen, T. & Kulmala, A., 2018, 2018 IEEE International Symposium on Circuits and Systems (ISCAS). IEEE, p. 1-5

    Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

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