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256-State Rate 1/2 Viterbi Decoder on TTA Processor

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Details

Original languageEnglish
Title of host publicationProceedings 2005 of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors, 23-25 July 2005, Samos Greece
EditorsS. Vassiliadis
Pages370-375
Publication statusPublished - 2005
Publication typeA4 Article in a conference publication

Publication forum classification