90 nm 32 × 32 bit tunneling SRAM memory array with 0.5 ns write access time, 1 ns read access time and 0.5 v operation
Research output: Contribution to journal › Article › Scientific › peer-review
Details
| Original language | English |
|---|---|
| Pages (from-to) | 2432-2445 |
| Number of pages | 14 |
| Journal | IEEE Transactions on Circuits and Systems. Part 1: Regular Papers |
| Volume | 58 |
| Issue number | 10 |
| DOIs | |
| Publication status | Published - 2011 |
| Publication type | A1 Journal article-refereed |
Abstract
Functional robustness is one of the primary challenges for embedded memories as voltage levels are scaled below 1 V. A low-power high-speed tunneling SRAM (TSRAM) memory array including sense amplifiers and pre-charge circuit blocks operating at 0.5 V is designed and simulated using available MOSIS CMOS 90 nm product design kit coupled with VerilogA models developed from this group's Si/SiGe resonant interband tunnel diode experimental data. 1 T and 3 T-2 tunnel diode memory cell configurations were evaluated. The memory array assigns 0.5 V as a logic 1 and 0 V as a logic 0. Dual supply voltages of 1 and 0.5 V and dual threshold voltage design are used to ensure high sensing speed concurrently with low operating and standby power. Read access time of 1 ns and write access time of 2 ns is achieved for the 3 T memory cell. Write access time can be reduced to 0.5 ns for 32 bit write operations not requiring a preceding read operation. Standby power dissipation of 6× 10-5mW per cell and dynamic power dissipation of &1.8× 10-7mW/MHz per cell is obtained from the TSRAM memory array. This is the first report of TSRAM performance at the array level.
ASJC Scopus subject areas
Keywords
- Embedded memory, low power memory, negative differential resistance (NDR), resonant interband tunnel diodes, tunnel diodes, tunnel static random access memory (SRAM)