A 122Mb/s Turbo decoder using a mid-range GPU
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
Standard
A 122Mb/s Turbo decoder using a mid-range GPU. / Xianjun, Jiao; Canfeng, Chen; Jääskeläinen, Pekka; Guzma, Vladimir; Berg, Heikki.
2013 9th International Wireless Communications and Mobile Computing Conference (IWCMC), 1-5 July 2013, Sardinia. Institute of Electrical and Electronics Engineers IEEE, 2013. p. 1090 - 1094 (International Wireless Communications and Mobile Computing Conference).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
Harvard
APA
Vancouver
Author
Bibtex - Download
}
RIS (suitable for import to EndNote) - Download
TY - GEN
T1 - A 122Mb/s Turbo decoder using a mid-range GPU
AU - Xianjun, Jiao
AU - Canfeng, Chen
AU - Jääskeläinen, Pekka
AU - Guzma, Vladimir
AU - Berg, Heikki
N1 - Contribution: organisation=tie,FACT1=1<br/>Portfolio EDEND: 2013-10-29<br/>Publisher name: Institute of Electrical and Electronics Engineers IEEE
PY - 2013
Y1 - 2013
N2 - Parallel implementations of Turbo decoding has been studied extensively. Traditionally, the number of parallel sub-decoders is limited to maintain acceptable code block error rate performance loss caused by the edge effect of code block division. In addition, the sub-decoders require synchronization to exchange information in the iterative process. In this paper, we propose loosening the synchronization between the sub-decoders to achieve higher utilization of parallel processor resources. Our method allows high degree of parallel processor utilization in decoding of a single code block providing a scalable software-based implementation. The proposed implementation is demonstrated using a graphics processing unit. We achieve 122.8Mbps decoding throughput using a medium range GPU, the Nvidia GTX480. This is, to the best of our knowledge, the fastest Turbo decoding throughput achieved with a GPU-based implementation.
AB - Parallel implementations of Turbo decoding has been studied extensively. Traditionally, the number of parallel sub-decoders is limited to maintain acceptable code block error rate performance loss caused by the edge effect of code block division. In addition, the sub-decoders require synchronization to exchange information in the iterative process. In this paper, we propose loosening the synchronization between the sub-decoders to achieve higher utilization of parallel processor resources. Our method allows high degree of parallel processor utilization in decoding of a single code block providing a scalable software-based implementation. The proposed implementation is demonstrated using a graphics processing unit. We achieve 122.8Mbps decoding throughput using a medium range GPU, the Nvidia GTX480. This is, to the best of our knowledge, the fastest Turbo decoding throughput achieved with a GPU-based implementation.
U2 - 10.1109/IWCMC.2013.6583709
DO - 10.1109/IWCMC.2013.6583709
M3 - Conference contribution
SN - 978-1-4673-2479-3
T3 - International Wireless Communications and Mobile Computing Conference
SP - 1090
EP - 1094
BT - 2013 9th International Wireless Communications and Mobile Computing Conference (IWCMC), 1-5 July 2013, Sardinia
PB - Institute of Electrical and Electronics Engineers IEEE
ER -