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A 30-dBm class-d power amplifier with On/Off logic for an integrated tri-phasing transmitter in 28-nm CMOS

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Details

Original languageEnglish
Title of host publicationProceedings of the 2018 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2018
PublisherIEEE
Pages136-139
Number of pages4
ISBN (Print)9781538645451
DOIs
Publication statusPublished - 7 Aug 2018
Publication typeA4 Article in a conference publication
EventIEEE Radio Frequency Integrated Circuits Symposium - Philadelphia, United States
Duration: 10 Jun 201812 Jun 2018

Publication series

Name
ISSN (Electronic)2375-0995

Conference

ConferenceIEEE Radio Frequency Integrated Circuits Symposium
CountryUnited States
CityPhiladelphia
Period10/06/1812/06/18

Abstract

This paper presents an eight-unit class-D power amplifier (PA), implemented in 28-nm CMOS. The PA is designed to utilize tri-phasing modulation, which combines coarse-amplitude polar modulation with fine-resolution outphasing components. This new technique enables achieving the back-off efficiency of multilevel outphasing without linearity-degrading discontinuities in the output waveform. Each PA unit contains a cascoded output stage with a 3.6-V supply voltage, and on/off logic enabling multilevel operation controlled by low-voltage signals. The PA achieves a peak output power of 29.7 dBm with a 34.7% efficiency, and is verified to operate with aggregated LTE signals at bandwidths up to 60 MHz at 1.7-GHz carrier frequency.

ASJC Scopus subject areas

Keywords

  • CMOS integrated circuits, outphasing, power amplifiers, radio transmitters, tri-phasing

Publication forum classification