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A 4.0/7.5-GHz Dual-Band LC VCO in 0.18-μm SiGe BiCMOS Technology

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A 4.0/7.5-GHz Dual-Band LC VCO in 0.18-μm SiGe BiCMOS Technology. / Jain, S.; Jang, S. L.; Juang, M. H.

International Symposium on VLSI Design, Automation and Test: VLSI-DAT. Vol. 30 2013.

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Harvard

Jain, S, Jang, SL & Juang, MH 2013, A 4.0/7.5-GHz Dual-Band LC VCO in 0.18-μm SiGe BiCMOS Technology. in International Symposium on VLSI Design, Automation and Test: VLSI-DAT. vol. 30. https://doi.org/10.1109/VLDI-DAT.2013.6533836

APA

Jain, S., Jang, S. L., & Juang, M. H. (2013). A 4.0/7.5-GHz Dual-Band LC VCO in 0.18-μm SiGe BiCMOS Technology. In International Symposium on VLSI Design, Automation and Test: VLSI-DAT (Vol. 30) https://doi.org/10.1109/VLDI-DAT.2013.6533836

Vancouver

Jain S, Jang SL, Juang MH. A 4.0/7.5-GHz Dual-Band LC VCO in 0.18-μm SiGe BiCMOS Technology. In International Symposium on VLSI Design, Automation and Test: VLSI-DAT. Vol. 30. 2013 https://doi.org/10.1109/VLDI-DAT.2013.6533836

Author

Jain, S. ; Jang, S. L. ; Juang, M. H. / A 4.0/7.5-GHz Dual-Band LC VCO in 0.18-μm SiGe BiCMOS Technology. International Symposium on VLSI Design, Automation and Test: VLSI-DAT. Vol. 30 2013.

Bibtex - Download

@inproceedings{7b77f6662bc14fa99711c6a63c91da95,
title = "A 4.0/7.5-GHz Dual-Band LC VCO in 0.18-μm SiGe BiCMOS Technology",
abstract = "This letter presents a low phase noise BiCMOS dual-band voltage-controlled oscillator (VCO). The designed circuit consists of a dual-resonance LC resonator and a Colpitts negative resistance cell. The dual-resonance LC resonator comprises a series-tuned LC resonator and a parallel resonant resonator. The proposed VCO has been implemented with the TSMC 0.18 μπι SiGe 3P6M BiCMOS process. The VCO can generate differential signals in the frequency range of 3.91∼4.17 GHz and 7.24∼7.80GHz with core power consumption is 6.30mW and 5.88mW at the dc bias of 1.4 V respectively. At 4.0 GHz and 7.74 GHz, phase noise at 1MHz offset is-121.13dBc/Hz and-115.87dBc/GHz respectively. The die area of the dual-band VCO is 0.485×0.800 mm2",
author = "S. Jain and Jang, {S. L.} and Juang, {M. H.}",
year = "2013",
month = "4",
day = "1",
doi = "10.1109/VLDI-DAT.2013.6533836",
language = "English",
volume = "30",
booktitle = "International Symposium on VLSI Design, Automation and Test",

}

RIS (suitable for import to EndNote) - Download

TY - GEN

T1 - A 4.0/7.5-GHz Dual-Band LC VCO in 0.18-μm SiGe BiCMOS Technology

AU - Jain, S.

AU - Jang, S. L.

AU - Juang, M. H.

PY - 2013/4/1

Y1 - 2013/4/1

N2 - This letter presents a low phase noise BiCMOS dual-band voltage-controlled oscillator (VCO). The designed circuit consists of a dual-resonance LC resonator and a Colpitts negative resistance cell. The dual-resonance LC resonator comprises a series-tuned LC resonator and a parallel resonant resonator. The proposed VCO has been implemented with the TSMC 0.18 μπι SiGe 3P6M BiCMOS process. The VCO can generate differential signals in the frequency range of 3.91∼4.17 GHz and 7.24∼7.80GHz with core power consumption is 6.30mW and 5.88mW at the dc bias of 1.4 V respectively. At 4.0 GHz and 7.74 GHz, phase noise at 1MHz offset is-121.13dBc/Hz and-115.87dBc/GHz respectively. The die area of the dual-band VCO is 0.485×0.800 mm2

AB - This letter presents a low phase noise BiCMOS dual-band voltage-controlled oscillator (VCO). The designed circuit consists of a dual-resonance LC resonator and a Colpitts negative resistance cell. The dual-resonance LC resonator comprises a series-tuned LC resonator and a parallel resonant resonator. The proposed VCO has been implemented with the TSMC 0.18 μπι SiGe 3P6M BiCMOS process. The VCO can generate differential signals in the frequency range of 3.91∼4.17 GHz and 7.24∼7.80GHz with core power consumption is 6.30mW and 5.88mW at the dc bias of 1.4 V respectively. At 4.0 GHz and 7.74 GHz, phase noise at 1MHz offset is-121.13dBc/Hz and-115.87dBc/GHz respectively. The die area of the dual-band VCO is 0.485×0.800 mm2

U2 - 10.1109/VLDI-DAT.2013.6533836

DO - 10.1109/VLDI-DAT.2013.6533836

M3 - Conference contribution

VL - 30

BT - International Symposium on VLSI Design, Automation and Test

ER -