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A brunch from the coffee table-case study in NOC platform design

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Details

Original languageEnglish
Title of host publicationInterconnect-Centric Design for Advanced SOC and NOC
EditorsJ. Nurmi, H. Tenhunen, J. Isoaho, A. Jantsch
Pages425-453
DOIs
Publication statusPublished - 2004
Publication typeA3 Part of a book or another research book

Abstract

As the non-recurring engineering costs of new technologies continue to rise, the importance of mass production grows. Mask costs in the million-dollar range are intolerable for low-volume products that are not targeted for high-end applications. On the other hand, Field Programmable Gate Arrays (FPGAs) are free from such costs, but feature a high unit cost. Beside this, interconnect delay and power consumption penalties in FPGAs may get prohibitively high for some applications. The gap to Application-Specific Integrated Circuits (ASICs) continues to widen in this sense, because wires dominate the performance of FPGAs. Interconnect downscaling increases resistance and sensitivity to electrical and mechanical stress, causing serious timing and reliability problems. These challenges in interconnect processing technology have incurred the fact that wire downscaling is not keeping up with the pace of logic downscaling. At the same time, decreasing wire spacing inevitably strengthens signal coupling effects between adjacent wires, which increases the level of uncertainty in functional correctness. On top of all that, there is considerable leakage current and hence leakage power due to thin isolation layers. The leakage current and interconnect effects together constitute the most important Deep SubMicron (DSM) effects that have to be taken into account already at an early stage of a design process of an ASIC. Obviously, something between ASICs and FPGAs is needed to simplify circuit design while keeping the cost and performance penalties to a minimum. For a more detailed discussion, refer to part 1: Physical and Electrical Issues. The DSM effects and the growing scale of Network-on-Chip (NoC) designs limit designer productivity by increasing the complexity of verification. NoCs are Systems-on-Chip (SoCs) that are implemented around an on-chip communication network rather than a bus. It is a wellestablished fact that designer productivity has not grown together with integration level and that there is little to gain by ever increasing the size of design teams. Team sizes between 8 and 15 people have been argued to be the most effective, while several such teams may be working on different aspects or abstraction levels of a single design. The use of predesigned and verified intellectual property (IP) blocks is being adopted to reduce the aforementioned problems. This increases designer productivity at the architectural level by pushing the required effort more towards system integration. Among other things, system integrators have to focus on interaction issues including communication requirements, compatibility of interfaces, correct co-functionality as well as successful technology migration. Thus a significant design effort is still needed. A natural step forward is to capture this effort for design reuse. Platform-based design enables better use of new technologies. Reuse of an existing NoC platform effectively lowers system design and manufacturing costs at the expense of a small efficiency overhead due to a more general purpose nature of the underlying hardware (HW). The problem of verification is essentially raised to the application level of abstraction as it has been solved for the lower abstraction levels during platform development. NoC platforms are composed of data acquisition and signal formation elements like Analog to Digital Converters (ADCs) and Digital to Analog Converters (DACs), memories, and processing elements (PEs) such as Digital Signal Processor (DSP) and Reduced Instruction Set Computer (RISC) cores. Equipped with a customized software (SW) environment including a real-time operating system(s) and a compiler(s), one design could effectively apply to a complete application domain. In many cases, however, the interconnection network forms the performance bottleneck of the system and therefore care should be taken in its design. The platform architecture design and customization processes should be automated with parameterizable IP libraries as the basis of such automation. Of the current efforts to automate platform design, the MESCAL (Modern Embedded Systems, Compilers, Architectures and Languages) project [2] is one of the most thorough. © 2005 Springer Science + Business Media, Inc.

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