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A low-power fractional decimator architecture for an IF-sampling dual-mode receiver

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Details

Original languageEnglish
Title of host publicationProceedings of 2004 IEEE International Symposium on Circuits and Systems, 23-26, May, 2004, Vancouver, British Columbia, Canada
Pages589-592
Publication statusPublished - 2004
Publication typeA4 Article in a conference publication

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