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A RTL asynchronous FIFO design using modified micropipeline

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Details

Original languageEnglish
Title of host publicationBEC 2006 - 2006 International Baltic Electronics Conference; Proceedings of the 10th Biennial Baltic Electronics Conference
Pages95-98
Number of pages4
DOIs
Publication statusPublished - 2006
Publication typeA4 Article in a conference publication
EventBEC 2006 - 2006 International Baltic Electronics Conference; 10th Biennial Batic Electronics Conference - Tallinn, Estonia
Duration: 2 Oct 20064 Oct 2006

Conference

ConferenceBEC 2006 - 2006 International Baltic Electronics Conference; 10th Biennial Batic Electronics Conference
CountryEstonia
CityTallinn
Period2/10/064/10/06

Abstract

An asynchronous FIFO which applies fourphase handshake protocol to read or write data has been designed in Register-Transfer Level (RTL) using VHDL. The asynchronous FIFO in this paper avoids data movement in a flow-through FIFO by applying token passing scheme in its control pipelines and multiplexer in its data register bank. Two control pipelines which base on micropipeline structure are proposed and used as the control logic for the asynchronous FIFO. An asynchronous arbiter and C-element RTL structures used in the proposed asynchronous FIFO are also presented.

ASJC Scopus subject areas