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AEx: Automated Customization of Exposed Datapath Soft-Cores

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Details

Original languageEnglish
Title of host publicationProceedings - Euromicro Conference on Digital System Design, DSD 2019
EditorsNikos Konofaos, Paris Kitsos
PublisherIEEE
Pages35-42
Number of pages8
ISBN (Electronic)9781728128610
DOIs
Publication statusPublished - Aug 2019
Publication typeA4 Article in a conference publication
EventEuromicro Conference on Digital System Design - Kallithea, Chalkidiki, Greece
Duration: 28 Aug 201930 Aug 2019

Publication series

NameProceedings - Euromicro Conference on Digital System Design, DSD 2019

Conference

ConferenceEuromicro Conference on Digital System Design
CountryGreece
CityKallithea, Chalkidiki
Period28/08/1930/08/19

Abstract

High-level synthesis tools aim to produce hardware designs out of software descriptions with a goal to lower the bar in FPGA usage for software engineers. Despite their recent progress, however, HLS tools still require FPGA target specific pragmas and other modifications to the originally processor-targeting source code descriptions. Customized soft core based overlay architectures provide a software programmable layer on top of the FPGA fabric. The benefit of this approach is that a platform independent compiler target is presented to the programs, which lowers the porting burden, and online repurposing the same configuration is natural by just switching the executed program. The main drawback, like with any overlay architecture, are the additional implementation overheads the overlay imposes to the resource consumption and the maximum operating frequency. In this paper we show how by utilizing the efficient structure of Transport-Triggered Architectures (TTA), soft-cores can be customized automatically to benefit from the flexible FPGA fabric while still presenting a comfortable software layer to the users. The results compared to previously published non-specialized TTA soft cores indicate equal or better execution times, while the program image size is reduced by up to 49%, and overall resource utilization improved from 10% to 60%.

Keywords

  • FPGA, high level synthesis, programmable overlays, soft cores, Transport-Triggered Architecture

Publication forum classification

Field of science, Statistics Finland