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ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA

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Details

Original languageEnglish
Pages (from-to)61-73
Number of pages13
JournalJournal of Signal Processing Systems
Volume91
Issue number1
DOIs
Publication statusPublished - 2 Jan 2019
Publication typeA1 Journal article-refereed

Abstract

The proliferation of processing hardware alternatives allows developers to use various customized computing platforms to run their applications in an optimal way. However, porting application code on custom hardware requires a lot of development and porting effort. This paper describes a heterogeneous computational platform (the ALMARVI execution platform) comprising of multiple communicating processors that allow easy programmability through an interface to OpenCL. The ALMARVI platform uses processing elements based on both VLIW and Transport Triggered Architectures (ρ-VEX and TCE cores, respectively). It can be implemented on Zynq devices such as the ZedBoard, and supports OpenCL by means of the pocl (Portable OpenCL) project and our ALMAIF interface specification. This allows developers to execute kernels transparently on either processing elements, thereby allowing to optimize execution time with minimal design and development effort.

Keywords

  • ALMARVI, OpenCL, pocl, TTA, TCE, rVEX, ZYNQ

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