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ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA

Research output: Contribution to journalArticleScientificpeer-review

Standard

ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA. / Hoozemans, Joost; van Straten, Jeroen; Viitanen, Timo; Tervo, Aleksi; Kadlec, Jiri; Al-Ars, Zaid.

In: Journal of Signal Processing Systems, Vol. 91, No. 1, 02.01.2019, p. 61-73.

Research output: Contribution to journalArticleScientificpeer-review

Harvard

Hoozemans, J, van Straten, J, Viitanen, T, Tervo, A, Kadlec, J & Al-Ars, Z 2019, 'ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA', Journal of Signal Processing Systems, vol. 91, no. 1, pp. 61-73. https://doi.org/10.1007/s11265-018-1424-1

APA

Hoozemans, J., van Straten, J., Viitanen, T., Tervo, A., Kadlec, J., & Al-Ars, Z. (2019). ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA. Journal of Signal Processing Systems, 91(1), 61-73. https://doi.org/10.1007/s11265-018-1424-1

Vancouver

Hoozemans J, van Straten J, Viitanen T, Tervo A, Kadlec J, Al-Ars Z. ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA. Journal of Signal Processing Systems. 2019 Jan 2;91(1):61-73. https://doi.org/10.1007/s11265-018-1424-1

Author

Hoozemans, Joost ; van Straten, Jeroen ; Viitanen, Timo ; Tervo, Aleksi ; Kadlec, Jiri ; Al-Ars, Zaid. / ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA. In: Journal of Signal Processing Systems. 2019 ; Vol. 91, No. 1. pp. 61-73.

Bibtex - Download

@article{82aa61dc7ec946199267fd68814c3012,
title = "ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA",
abstract = "The proliferation of processing hardware alternatives allows developers to use various customized computing platforms to run their applications in an optimal way. However, porting application code on custom hardware requires a lot of development and porting effort. This paper describes a heterogeneous computational platform (the ALMARVI execution platform) comprising of multiple communicating processors that allow easy programmability through an interface to OpenCL. The ALMARVI platform uses processing elements based on both VLIW and Transport Triggered Architectures (ρ-VEX and TCE cores, respectively). It can be implemented on Zynq devices such as the ZedBoard, and supports OpenCL by means of the pocl (Portable OpenCL) project and our ALMAIF interface specification. This allows developers to execute kernels transparently on either processing elements, thereby allowing to optimize execution time with minimal design and development effort.",
keywords = "ALMARVI, OpenCL, pocl, TTA, TCE, rVEX, ZYNQ",
author = "Joost Hoozemans and {van Straten}, Jeroen and Timo Viitanen and Aleksi Tervo and Jiri Kadlec and Zaid Al-Ars",
year = "2019",
month = "1",
day = "2",
doi = "10.1007/s11265-018-1424-1",
language = "English",
volume = "91",
pages = "61--73",
journal = "Journal of Signal Processing Systems",
issn = "1939-8018",
publisher = "Springer Verlag",
number = "1",

}

RIS (suitable for import to EndNote) - Download

TY - JOUR

T1 - ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA

AU - Hoozemans, Joost

AU - van Straten, Jeroen

AU - Viitanen, Timo

AU - Tervo, Aleksi

AU - Kadlec, Jiri

AU - Al-Ars, Zaid

PY - 2019/1/2

Y1 - 2019/1/2

N2 - The proliferation of processing hardware alternatives allows developers to use various customized computing platforms to run their applications in an optimal way. However, porting application code on custom hardware requires a lot of development and porting effort. This paper describes a heterogeneous computational platform (the ALMARVI execution platform) comprising of multiple communicating processors that allow easy programmability through an interface to OpenCL. The ALMARVI platform uses processing elements based on both VLIW and Transport Triggered Architectures (ρ-VEX and TCE cores, respectively). It can be implemented on Zynq devices such as the ZedBoard, and supports OpenCL by means of the pocl (Portable OpenCL) project and our ALMAIF interface specification. This allows developers to execute kernels transparently on either processing elements, thereby allowing to optimize execution time with minimal design and development effort.

AB - The proliferation of processing hardware alternatives allows developers to use various customized computing platforms to run their applications in an optimal way. However, porting application code on custom hardware requires a lot of development and porting effort. This paper describes a heterogeneous computational platform (the ALMARVI execution platform) comprising of multiple communicating processors that allow easy programmability through an interface to OpenCL. The ALMARVI platform uses processing elements based on both VLIW and Transport Triggered Architectures (ρ-VEX and TCE cores, respectively). It can be implemented on Zynq devices such as the ZedBoard, and supports OpenCL by means of the pocl (Portable OpenCL) project and our ALMAIF interface specification. This allows developers to execute kernels transparently on either processing elements, thereby allowing to optimize execution time with minimal design and development effort.

KW - ALMARVI

KW - OpenCL

KW - pocl

KW - TTA

KW - TCE

KW - rVEX

KW - ZYNQ

U2 - 10.1007/s11265-018-1424-1

DO - 10.1007/s11265-018-1424-1

M3 - Article

VL - 91

SP - 61

EP - 73

JO - Journal of Signal Processing Systems

JF - Journal of Signal Processing Systems

SN - 1939-8018

IS - 1

ER -