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An Explicitly Parallel Architecture for Packet Parsing in Software Defined Networks

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Details

Original languageEnglish
Title of host publication2018 IEEE 29th International Conference on Application-specific Systems, Architectures and Processors (ASAP)
PublisherIEEE
Number of pages4
ISBN (Print)978-1-5386-7479-6
DOIs
Publication statusPublished - 23 Aug 2018
Publication typeA4 Article in a conference publication
EventIEEE International Conference on Application-specific Systems, Architectures and Processors -
Duration: 10 Jul 201812 Jul 2018

Publication series

Name IEEE International Conference on Application-Specific Systems, Architectures, and Processors
ISSN (Print)2160-0511
ISSN (Electronic)2160-052X

Conference

ConferenceIEEE International Conference on Application-specific Systems, Architectures and Processors
Period10/07/1812/07/18

Abstract

Packet parsing is the first step in processing of packets in devices such as network switches and routers. The process of packet parsing has become more challenging due to the increase in line rates and emergence of Software Defined Networking which leads to new protocols being adopted. In this paper, we present a novel architecture for parsing of packets. The architecture is fully programmable and is not tied to any specific protocol. It can be programmed to parse any protocol making it suitable for Software Defined Networks. Compared with the parser used in the Reconfigurable Match Tables, our parser improves supported throughput by a factor of 3.2. Moreover, to achieve the target throughput of 640 Gbps, our parser needs only 2 percent of the number of gates used in the parsers of Reconfigurable Match Tables.