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An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks

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Details

Original languageEnglish
Title of host publication2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
EditorsJari Nurmi, Peeter Ellervee, Kari Halonen, Juha Röning
PublisherIEEE
ISBN (Electronic)978-1-7281-2769-9
ISBN (Print)978-1-7281-2770-5
DOIs
Publication statusPublished - 29 Oct 2019
Publication typeA4 Article in a conference publication
EventIEEE Nordic Circuits and Systems Conference -
Duration: 1 Jan 2000 → …

Conference

ConferenceIEEE Nordic Circuits and Systems Conference
Period1/01/00 → …

Abstract

Programmable data plane is a key enabler of Software Defined Networking. By making networking devices programmable, novel networking services and functions could be realized by means of software running on these devices. In this paper, we present a lightweight packet processor that could process the packets on the fly as they arrive. As we will see, the area of this packet processor is smaller than a packet parser employing Ternary Content Addressable Memory. As an added benefit, the designed packet processor could also reduce the traffic to the lookup tables on the chip. Moreover, its use is not limited to switches and routers. It could also be used in the Network Interface Cards and offload packet processing tasks. Despite its packet processing capabilities, packet processor instances required for sustaining aggregate throughput of 640 Gbps have area equivalent to the packet parser instances in the Reconfigurable Match Tables Architecture.

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