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An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Standard

An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks. / Zolfaghari, Hesam; Rossi, Davide; Nurmi, Jari.

2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). ed. / Jari Nurmi; Peeter Ellervee; Kari Halonen; Juha Röning. IEEE, 2019.

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Harvard

Zolfaghari, H, Rossi, D & Nurmi, J 2019, An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks. in J Nurmi, P Ellervee, K Halonen & J Röning (eds), 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE, IEEE Nordic Circuits and Systems Conference, 1/01/00. https://doi.org/10.1109/NORCHIP.2019.8906959

APA

Zolfaghari, H., Rossi, D., & Nurmi, J. (2019). An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks. In J. Nurmi, P. Ellervee, K. Halonen, & J. Röning (Eds.), 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC) IEEE. https://doi.org/10.1109/NORCHIP.2019.8906959

Vancouver

Zolfaghari H, Rossi D, Nurmi J. An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks. In Nurmi J, Ellervee P, Halonen K, Röning J, editors, 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). IEEE. 2019 https://doi.org/10.1109/NORCHIP.2019.8906959

Author

Zolfaghari, Hesam ; Rossi, Davide ; Nurmi, Jari. / An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks. 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC). editor / Jari Nurmi ; Peeter Ellervee ; Kari Halonen ; Juha Röning. IEEE, 2019.

Bibtex - Download

@inproceedings{a847cdf171384ea1a446b9bc4cc9a59f,
title = "An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks",
abstract = "Programmable data plane is a key enabler of Software Defined Networking. By making networking devices programmable, novel networking services and functions could be realized by means of software running on these devices. In this paper, we present a lightweight packet processor that could process the packets on the fly as they arrive. As we will see, the area of this packet processor is smaller than a packet parser employing Ternary Content Addressable Memory. As an added benefit, the designed packet processor could also reduce the traffic to the lookup tables on the chip. Moreover, its use is not limited to switches and routers. It could also be used in the Network Interface Cards and offload packet processing tasks. Despite its packet processing capabilities, packet processor instances required for sustaining aggregate throughput of 640 Gbps have area equivalent to the packet parser instances in the Reconfigurable Match Tables Architecture.",
author = "Hesam Zolfaghari and Davide Rossi and Jari Nurmi",
year = "2019",
month = "10",
day = "29",
doi = "10.1109/NORCHIP.2019.8906959",
language = "English",
isbn = "978-1-7281-2770-5",
editor = "Jari Nurmi and Peeter Ellervee and Kari Halonen and Juha R{\"o}ning",
booktitle = "2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)",
publisher = "IEEE",

}

RIS (suitable for import to EndNote) - Download

TY - GEN

T1 - An Explicitly Parallel Architecture for Packet Processing in Software Defined Networks

AU - Zolfaghari, Hesam

AU - Rossi, Davide

AU - Nurmi, Jari

PY - 2019/10/29

Y1 - 2019/10/29

N2 - Programmable data plane is a key enabler of Software Defined Networking. By making networking devices programmable, novel networking services and functions could be realized by means of software running on these devices. In this paper, we present a lightweight packet processor that could process the packets on the fly as they arrive. As we will see, the area of this packet processor is smaller than a packet parser employing Ternary Content Addressable Memory. As an added benefit, the designed packet processor could also reduce the traffic to the lookup tables on the chip. Moreover, its use is not limited to switches and routers. It could also be used in the Network Interface Cards and offload packet processing tasks. Despite its packet processing capabilities, packet processor instances required for sustaining aggregate throughput of 640 Gbps have area equivalent to the packet parser instances in the Reconfigurable Match Tables Architecture.

AB - Programmable data plane is a key enabler of Software Defined Networking. By making networking devices programmable, novel networking services and functions could be realized by means of software running on these devices. In this paper, we present a lightweight packet processor that could process the packets on the fly as they arrive. As we will see, the area of this packet processor is smaller than a packet parser employing Ternary Content Addressable Memory. As an added benefit, the designed packet processor could also reduce the traffic to the lookup tables on the chip. Moreover, its use is not limited to switches and routers. It could also be used in the Network Interface Cards and offload packet processing tasks. Despite its packet processing capabilities, packet processor instances required for sustaining aggregate throughput of 640 Gbps have area equivalent to the packet parser instances in the Reconfigurable Match Tables Architecture.

U2 - 10.1109/NORCHIP.2019.8906959

DO - 10.1109/NORCHIP.2019.8906959

M3 - Conference contribution

SN - 978-1-7281-2770-5

BT - 2019 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

A2 - Nurmi, Jari

A2 - Ellervee, Peeter

A2 - Halonen, Kari

A2 - Röning, Juha

PB - IEEE

ER -