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Applying the adaptive hybrid flow-Shop scheduling method to schedule a 3GPP LTE physical layer algorithm onto many-core digital signal processors

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review


Original languageEnglish
Title of host publicationProceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2013
Number of pages7
Publication statusPublished - 2013
Publication typeA4 Article in a conference publication
Event2013 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2013 - Turin, Italy
Duration: 25 Jun 201327 Jun 2013


Conference2013 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2013


Currently, Multicore Digital Signal Processor (DSP) platforms are commonly used in telecommunications baseband processing. In the next few years, high performance DSPs are likely to combine many more DSP cores for signal processing with some General-Purpose Processor (GPP) cores for application control. As the number of cores increases in new DSP platform designs, scheduling of applications is becoming a complex operation. Meanwhile, the variability of the scheduled applications also tends to increase as applications become more sophisticated. Such variations require runtime adaptivity of application scheduling. This paper extends the previous work on adaptive scheduling by using the Hybrid Flow-Shop (HFS) scheduling method, which enables the device architecture to be modeled as a pipeline of Processing Elements (PEs) with multiple alternate PEs for each pipeline stage. HFS scheduling is applied to the scheduling of 3rd Generation Partnership Project (3GPP) Long Term Evolution (LTE) telecommunication standard Uplink Physical Layer data processing (PUSCH). The experiments, conducted on an ARM Cortex-A9 GPP, show that an HFS scheduling algorithm has an overhead that increases very slowly with the number of PEs. This makes the method suitable for executing the adaptive scheduling in less than 1 ms for the 501 actors of a LTE PUSCH dataflow description executed on a 256-core architecture.