Tampere University of Technology

TUTCRIS Research Portal

ATM switch for 2.488 Gbit/s CATV network on FPGA with a high-throughput buffering architecture

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review


Original languageEnglish
Title of host publicationMidwest Symposium on Circuits and Systems
Publication statusPublished - 2002
Publication typeA4 Article in a conference publication
Event2002 45th Midwest Symposium on Circuits and Systems - Tulsa, OK, United States
Duration: 4 Aug 20027 Aug 2002


Conference2002 45th Midwest Symposium on Circuits and Systems
CountryUnited States
CityTulsa, OK


This paper presents an ATM switch with a high-throughput buffering architecture and a new performance measurement system. The switch has been designed for multiplexing and routing Digital Video Broadcasting (DVB) services over 2.488 Gbits/s Asynchronous Transfer Mode (ATM) Cable TV (CATV) backbone network. The buffering architecture is based on a crossbar switch with internal buffering but it also has features of shared memory and output buffered switches. In addition to the buffering architecture the high throughput of this switch is based on an adaptive arbitration algorithm that is used to schedule the transfers of the cells from the cross-point buffers to the output buffers. This adaptive algorithm, which is a combination of Round Robin (RR) and Longest Queue First Served (LQFS) algorithms, provides starvation free service for the buffers with a small cell loss rate. Due to the internal buffering it was possible to use distributed arbitration that can easier achieve a high operation rate than one centralized arbiter. This paper also shows a quick and easy way of analyzing the performance of the presented ATM switch architecture. The high throughput of the switch has also been verified using a new method of measuring the probability distribution of the filling of the buffers of the switch. Additionally this paper deals with a few implementation aspects, since the control logic and the internally buffered crossbar are implemented on a Field Programmable Gate Array (FPGA) circuit.