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Automatic synthesis of TTA processor networks from RVC-CAL dataflow programs

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Details

Original languageEnglish
Title of host publication2011 IEEE Workshop on Signal Processing Systems, SiPS 2011, Proceedings
Pages25-30
Number of pages6
DOIs
Publication statusPublished - 2011
Publication typeA4 Article in a conference publication
Event2011 IEEE Workshop on Signal Processing Systems, SiPS 2011 - Beirut, Lebanon
Duration: 4 Oct 20117 Oct 2011

Conference

Conference2011 IEEE Workshop on Signal Processing Systems, SiPS 2011
CountryLebanon
CityBeirut
Period4/10/117/10/11

Abstract

The RVC-CAL dataflow language has recently become standardized through its use as the official language of Recon-figurable Video Coding (RVC), a recent standard by MPEG. The tools developed for RVC-CAL have enabled the transformation of RVC-CAL dataflow programs into C language and VHDL (among others), enabling implementations for instruction processors and HDL synthesis. This paper introduces new tools that enable automatic creation of heterogeneous multiprocessor networks out of RVC-CAL dataflow programs. Each processor in the network performs the functionality of one RVC-CAL actor. The processors are of the Transport Triggered Architecture (TTA) type, for which a complete co-design toolset exists. The existing tools enable customizing the processors according to the requirements of individual dataflow actors. The functionality of the tool chain has been demonstrated by synthesizing an MPEG-4 Simple Profile video decoder to an FPGA. This particular decoder is automatically realized into 21 tiny, heterogeneous processors.

ASJC Scopus subject areas

Keywords

  • data flow computing, design automation, multiprocessor interconnection