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Benchmarking of nanometer technologies for DPA-resilient DPL-based cryptocircuits

Research output: Other conference contributionPaper, poster or abstractScientific

Details

Original languageEnglish
Number of pages6
DOIs
Publication statusPublished - 4 Apr 2019
Externally publishedYes
Publication typeNot Eligible
Event2018 Conference on Design of Circuits and Integrated Systems - Lyon, France
Duration: 14 Nov 201816 Nov 2018
Conference number: XXIII

Conference

Conference2018 Conference on Design of Circuits and Integrated Systems
Abbreviated titleDCIS
CountryFrance
CityLyon
Period14/11/1816/11/18

Abstract

The design of cryptographic circuits is requiring greater performance restrictions due to the constrained environments for IoT applications in which they are included. Focusing on the countermeasures based on dual-precharge logic styles, power, area and delay penalties are some of their major drawbacks when compared to their static CMOS single-ended counterparts. In this paper, we propose a initial study where scaled CMOS technnology and FinFET emerging technology are considered to foresee the relationship between ultra low power consumption, reduced delay, and security. As demonstration vehicle, we measure the performance and the security level achieved by different Substitution Boxes, implemented in different technologies. As main results, nanometer CMOS technologies maintains considerable security levels at reasonable power and delay figures, while FinFETs outperform CMOS in power and delay reduction, but with a non negligible degradation in security.