Tampere University of Technology

TUTCRIS Research Portal

Cache-Timing Attacks on RSA Key Generation

Research output: Contribution to journalArticleScientificpeer-review

Details

Original languageEnglish
Pages (from-to)213-242
Number of pages30
JournalIACR Transactions on Cryptographic Hardware and Embedded Systems (TCHES)
Volume2019
Issue number4
DOIs
Publication statusPublished - 2019
Publication typeA1 Journal article-refereed

Abstract

During the last decade, constant-time cryptographic software has quickly transitioned from an academic construct to a concrete security requirement for real-world libraries. Most of OpenSSL’s constant-time code paths are driven by cryptosystem implementations enabling a dedicated flag at runtime. This process is perilous, with several examples emerging in the past few years of the flag either not being set or software defects directly mishandling the flag. In this work, we propose a methodology to analyze security-critical software for side-channel insecure code path traversal. Applying our methodology to OpenSSL, we identify three new code paths during RSA key generation that potentially leak critical algorithm state. Exploiting one of these leaks, we design, implement, and mount a single trace cache-timing attack on the GCD computation step. We overcome several hurdles in the process, including but not limited to: (1) granularity issues due to word-size operands to the GCD function; (2) bulk processing of desynchronized trace data; (3) non-trivial error rate during information extraction; and (4) limited high-confidence information on the modulus factors. Formulating lattice problem instances after obtaining and processing this limited information, our attack achieves roughly a 27% success rate for key recovery using the empirical data from 10K trials.

Keywords

  • Applied cryptography, public key cryptography, RSA, Side-channel analysis, timing attacks, cache-timing attacks, OpenSSL, CVE-2018-0737

Publication forum classification

Field of science, Statistics Finland