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Class D CMOS power amplifier with on/off logic for a multilevel outphasing transmitter

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Details

Original languageEnglish
Title of host publicationISCAS 2016 - IEEE International Symposium on Circuits and Systems
PublisherIEEE
Pages710-713
Number of pages4
ISBN (Electronic)9781479953400
DOIs
Publication statusPublished - 29 Jul 2016
Publication typeA4 Article in a conference publication
EventIEEE International Symposium on Circuits and Systems -
Duration: 1 Jan 1900 → …

Publication series

Name
ISSN (Electronic)2379-447X

Conference

ConferenceIEEE International Symposium on Circuits and Systems
Period1/01/00 → …

Abstract

In this paper, we present a class D power amplifier (PA) design in 28 nm CMOS for a multilevel outphasing transmitter. For increased output power, the design consists of eight unit PAs with cascoded output stages. In order to improve back-off efficiency from conventional outphasing, the PAs are switched on and off in pairs for different amplitude levels, which is challenging to implement with cascoded class D. As a solution, we introduce a new on/off switching method based on logic gates utilizing two square wave voltages to produce either a similar square wave or a constant voltage. This method enables a higher level of integration by using low-voltage digital signals for on/off control, while eliminating the timing mismatch between output transistors caused by a level shifter. The simulated peak output power of the PA is 32.4 dBm, and its peak efficiency is 34.1%.

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