Configurable, resource-optimized FFT architecture for OFDM communication
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
Details
| Original language | English |
|---|---|
| Title of host publication | 2013 IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2013 - Proceedings |
| Pages | 2746-2750 |
| Number of pages | 5 |
| DOIs | |
| Publication status | Published - 18 Oct 2013 |
| Publication type | A4 Article in a conference publication |
| Event | 2013 38th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2013 - Vancouver, BC, Canada Duration: 26 May 2013 → 31 May 2013 |
Conference
| Conference | 2013 38th IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2013 |
|---|---|
| Country | Canada |
| City | Vancouver, BC |
| Period | 26/05/13 → 31/05/13 |
Abstract
In this paper, we present a designer-configurable, resource efficient FPGA architecture for OFDM system implementation. Our design achieves a significant improvement in resource efficiency for a given data rate. This efficiency improvement is achieved through careful analysis of how FFT computation is performed within the context of OFDM systems, and streamlining memory management and control logic based on this analysis. In particular, our OFDM-targeted FFT design eliminates redundant buffer memory, and simplifies control logic to save FPGA resources. We have synthesized and tested our design using the Xilinx ISE 13.4 synthesis tool, and compared the results with the Xilinx FFT v7.1, which is a widely used commercial FPGA IP core. We have demonstrated that our design provides at least 8.8% enhancement in terms of resource efficiency compared to Xilinx FFT v7.1 when it is embedded within the same OFDM configuration.
ASJC Scopus subject areas
Keywords
- FFT, FPGA, OFDM, Resource