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Customized exposed datapath soft-core design flow with compiler support

Research output: Scientific - peer-reviewConference contribution

Standard

Customized exposed datapath soft-core design flow with compiler support. / Esko, Otto; Jääskeläinen, Pekka; Huerta, Pablo; de La Lama, Carlos S.; Takala, Jarmo; Martinez, Jose Ignacio.

2010 International Conference on Field Programmable Logic and Applications, 31 August - 2 September, 2010, Milano, Italy. 2010. p. 217-222.

Research output: Scientific - peer-reviewConference contribution

Harvard

Esko, O, Jääskeläinen, P, Huerta, P, de La Lama, CS, Takala, J & Martinez, JI 2010, Customized exposed datapath soft-core design flow with compiler support. in 2010 International Conference on Field Programmable Logic and Applications, 31 August - 2 September, 2010, Milano, Italy. pp. 217-222. DOI: 10.1109/FPL.2010.51

APA

Esko, O., Jääskeläinen, P., Huerta, P., de La Lama, C. S., Takala, J., & Martinez, J. I. (2010). Customized exposed datapath soft-core design flow with compiler support. In 2010 International Conference on Field Programmable Logic and Applications, 31 August - 2 September, 2010, Milano, Italy (pp. 217-222). DOI: 10.1109/FPL.2010.51

Vancouver

Esko O, Jääskeläinen P, Huerta P, de La Lama CS, Takala J, Martinez JI. Customized exposed datapath soft-core design flow with compiler support. In 2010 International Conference on Field Programmable Logic and Applications, 31 August - 2 September, 2010, Milano, Italy. 2010. p. 217-222. Available from, DOI: 10.1109/FPL.2010.51

Author

Esko, Otto; Jääskeläinen, Pekka; Huerta, Pablo; de La Lama, Carlos S.; Takala, Jarmo; Martinez, Jose Ignacio / Customized exposed datapath soft-core design flow with compiler support.

2010 International Conference on Field Programmable Logic and Applications, 31 August - 2 September, 2010, Milano, Italy. 2010. p. 217-222.

Research output: Scientific - peer-reviewConference contribution

Bibtex - Download

@inbook{ceafc4c3966d451d95db2e4f73c9abd1,
title = "Customized exposed datapath soft-core design flow with compiler support",
abstract = "A popular way to exploit high level programming languages in FPGA designs is to use a soft-core with accompanying software development tools. However, a common shortcoming with the current soft-core offerings is their limited software execution capability: the required performance for the implementation can be often reached only with instruction set extensions. In this paper, we propose and evaluate an application-specific processor design toolset that uses a multi-issue exposed data path processor architecture template. The main benefit of the architecture is scalability with respect to instruction-level parallelism (ILP). The design flow allows the designer to freely customize the data path resources in the core to exploit the ILP available in computation intensive kernels. The design toolset includes a retargetable C compiler and an architecture simulator, making design space exploration feasible. The experiments show that a relatively small soft-core tailored with the toolset provides significant speedups on software execution without using any instruction set extensions. The best measured speedup in comparison to the major commercial soft-cores was fourfold in applications from the CHStone benchmark suite, while the amount of consumed FPGA resources remained moderate.",
author = "Otto Esko and Pekka Jääskeläinen and Pablo Huerta and {de La Lama}, {Carlos S.} and Jarmo Takala and Martinez, {Jose Ignacio}",
note = "Contribution: organisation=tkt,FACT1=1",
year = "2010",
doi = "10.1109/FPL.2010.51",
isbn = "978-0-7695-4179-2",
pages = "217--222",
booktitle = "2010 International Conference on Field Programmable Logic and Applications, 31 August - 2 September, 2010, Milano, Italy",

}

RIS (suitable for import to EndNote) - Download

TY - CHAP

T1 - Customized exposed datapath soft-core design flow with compiler support

AU - Esko,Otto

AU - Jääskeläinen,Pekka

AU - Huerta,Pablo

AU - de La Lama,Carlos S.

AU - Takala,Jarmo

AU - Martinez,Jose Ignacio

N1 - Contribution: organisation=tkt,FACT1=1

PY - 2010

Y1 - 2010

N2 - A popular way to exploit high level programming languages in FPGA designs is to use a soft-core with accompanying software development tools. However, a common shortcoming with the current soft-core offerings is their limited software execution capability: the required performance for the implementation can be often reached only with instruction set extensions. In this paper, we propose and evaluate an application-specific processor design toolset that uses a multi-issue exposed data path processor architecture template. The main benefit of the architecture is scalability with respect to instruction-level parallelism (ILP). The design flow allows the designer to freely customize the data path resources in the core to exploit the ILP available in computation intensive kernels. The design toolset includes a retargetable C compiler and an architecture simulator, making design space exploration feasible. The experiments show that a relatively small soft-core tailored with the toolset provides significant speedups on software execution without using any instruction set extensions. The best measured speedup in comparison to the major commercial soft-cores was fourfold in applications from the CHStone benchmark suite, while the amount of consumed FPGA resources remained moderate.

AB - A popular way to exploit high level programming languages in FPGA designs is to use a soft-core with accompanying software development tools. However, a common shortcoming with the current soft-core offerings is their limited software execution capability: the required performance for the implementation can be often reached only with instruction set extensions. In this paper, we propose and evaluate an application-specific processor design toolset that uses a multi-issue exposed data path processor architecture template. The main benefit of the architecture is scalability with respect to instruction-level parallelism (ILP). The design flow allows the designer to freely customize the data path resources in the core to exploit the ILP available in computation intensive kernels. The design toolset includes a retargetable C compiler and an architecture simulator, making design space exploration feasible. The experiments show that a relatively small soft-core tailored with the toolset provides significant speedups on software execution without using any instruction set extensions. The best measured speedup in comparison to the major commercial soft-cores was fourfold in applications from the CHStone benchmark suite, while the amount of consumed FPGA resources remained moderate.

U2 - 10.1109/FPL.2010.51

DO - 10.1109/FPL.2010.51

M3 - Conference contribution

SN - 978-0-7695-4179-2

SP - 217

EP - 222

BT - 2010 International Conference on Field Programmable Logic and Applications, 31 August - 2 September, 2010, Milano, Italy

ER -