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Data Rate Assessment on L2–L3 CPU Bus and Bus between CPU and RAM in Modern CPUs

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Details

Original languageEnglish
Pages (from-to)701-708
Number of pages8
JournalAutomatic Control and Computer Sciences
Volume51
Issue number7
DOIs
Publication statusPublished - 2017
Publication typeA1 Journal article-refereed

Abstract

In this paper, modern CPU architecture with several different cache levels is described and current CPU performance limitations such as frequency increase bounds are discussed. As changes to the currently existing architecture are usually proposed as a way of increasing CPU performance, data rates of the internal and external CPU interfaces must be known. This information would help to assess the applicability of proposed solutions and to optimize them. This paper is aimed at obtaining real values of traffic on an L2–L3 cache interface inside a CPU and a CPU–RAM bus load, as well as showing the dependences of the total traffic on the studied interfaces on the number of active cores, CPU frequency, and test type. A measurement methodology using an Intel Performance Counter Monitor is provided and the equations used to obtain data rates from the internal CPU counters are explained. Both real-life and synthetic tests are described. The dependence of total traffic on the number of active cores and the dependence of total traffic on CPU frequency are provided as plots. The dependence of total traffic on test type is provided as a bar plot for multiple CPU frequencies.

Keywords

  • data rate assessment, multicore CPUs, Network-on-Chip, NoC, System-on-Chip, Wireless Network- on-Chip, WNoC

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