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Design and Implementation of IEEE 802.11a/g Receiver Blocks on a Coarse-Grained Reconfigurable Array

Research output: Chapter in Book/Report/Conference proceedingChapterScientificpeer-review


Original languageEnglish
Title of host publicationComputing Platforms for Software-Defined Radio
EditorsWaqar Hussain, Jari Nurmi, Jouni Isoaho, Fabio Garzia
ISBN (Electronic)978-3-319-49679-5
ISBN (Print)978-3-319-49678-8
Publication statusPublished - 2017
Publication typeA3 Part of a book or another research book


This chapter presents the design and evaluation of template-based Coarse-Grained Reconfigurable Array (CGRA) generated accelerators that process Orthogonal Frequency-Division Multiplexing receiver blocks. The CGRA operates as a coprocessor with a Reduced Instruction-Set Computing (RISC) processor so that the overall system yields the benefits of general- and special-purpose processing. The accelerators are designed by crafting the CGRA template to the computational and communication requirements of the algorithms in an effort to minimize the resource utilization and power dissipation on the target Field Programmable Gate Array (FPGA) device. The performance of each CGRA is recorded in terms of the number of clock cycles and several multiple performance metrics. The power consumption is also estimated by simulating the postfit gate-level FPGA netlist of the accelerators.

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