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Design space exploration and implementation of RVC-CAL applications using the TURNUS framework

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review


Original languageEnglish
Title of host publicationDASIP 2013 - Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing
Number of pages2
Publication statusPublished - 2013
Publication typeA4 Article in a conference publication
Event2013 7th Conference on Design and Architectures for Signal and Image Processing, DASIP 2013 - Cagliari, Italy
Duration: 8 Oct 201310 Oct 2013


Conference2013 7th Conference on Design and Architectures for Signal and Image Processing, DASIP 2013


While research on the design of heterogeneous concurrent systems has a long and rich history, a unified design methodology and tool support has not emerged so far, and thus the creation of such systems remains a difficult, time-consuming and error-prone process. The absence of principled support for system evaluation and optimization at high abstraction levels makes the quality of the resulting implementation highly dependent on the experience or prejudices of the designer. In this work we present TURNUS, a unified dataflow design space exploration framework for heterogeneous parallel systems. It provides high-level modelling and simulation methods and tools for system level performances estimation and optimization. TURNUS represents the outcome of several years of research in the area of co-design exploration for multimedia stream applications. During the presentation, it will be demonstrated how the initial high-level abstraction of the design facilitates the use of different analysis and optimization heuristics. These guide the designer during validation and optimization stages without requiring low-level implementations of parts of the application. Our framework currently yields exploration and optimization results in terms of algorithmic optimization, rapid performance estimation, application throughput, buffer size dimensioning, and power optimization.