Exposed Datapath optimizations for Loop Scheduling
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
Details
| Original language | English |
|---|---|
| Title of host publication | Embedded Computer Systems: Architectures, Modeling, and Simulation 2017 IEEE International Conference (IC-SAMOS 2017) |
| Publisher | IEEE |
| Pages | 171-178 |
| Number of pages | 8 |
| ISBN (Electronic) | 978-1-5386-3437-0 |
| DOIs | |
| Publication status | Published - 2018 |
| Publication type | A4 Article in a conference publication |
| Event | International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation - Duration: 1 Jan 1900 → … |
Conference
| Conference | International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation |
|---|---|
| Period | 1/01/00 → … |
Abstract
Transport Triggered Architecture (TTA) processors allow unique low level compiler optimizations such as software bypassing and operand sharing. Previously, these optimizations have mostly been performed inside single basic blocks, leaving much of their potential unused. In this work, software bypassing and operand sharing are integrated with loop scheduling, allowing optimizations over loop iteration boundaries. This considerably further reduces register file accesses and immediate value transfers on tight loops – in some cases even eliminating all register file accesses from the loop body. In the benchmarked 12 small loops, compared to traditional VLIW-style processors, on average 63% of register file reads and 77% of register file writes could be eliminated. Compared to a compiler which performs these optimizations only inside a basic block, on average 58% of register file reads, 28% of register file writes could be eliminated. The additional register access reductions allow both direct energy savings from fewer register accesses and indirect energy savings by allowing the use of simpler register files with less read and write ports and a simpler interconnect network with less transport buses.
ASJC Scopus subject areas
Publication forum classification
Field of science, Statistics Finland
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