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Feasibility of FPGA accelerated IPsec on cloud

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Details

Original languageEnglish
Title of host publication2018 Euromicro Conference on Digital System Design (DSD)
PublisherIEEE
ISBN (Electronic)978-1-5386-7377-5
DOIs
Publication statusPublished - 31 Aug 2018
Publication typeA4 Article in a conference publication
EventEuromicro Conference on Digital System Design - Prague, Czech Republic
Duration: 29 Aug 201831 Aug 2018

Conference

ConferenceEuromicro Conference on Digital System Design
CountryCzech Republic
CityPrague
Period29/08/1831/08/18

Abstract

Line-rate speed requirements for performance hungry network applications like IPsec are getting problematic due to the virtualization trend. A single virtual network application hardly can provide 40 Gbps operation. This research considers the IPsec packet processing without IKE to be offloaded on an FPGA in a network. We propose an IPsec accelerator in an FPGA and explain the details that need to be considered for a production ready design. Based on our evaluation, Intel Arria 10 FPGA can provide 10 Gbps line-rate operation for the IPsec accelerator and to be responsible for 1000 IPsec tunnels. The research points out that for future data centers it is beneficial to rely on HW acceleration in terms of speed and energy efficiency for applications like IPsec.

Publication forum classification

Field of science, Statistics Finland