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Flexible software-defined packet processing using low-area hardware

Research output: Contribution to journalArticleScientificpeer-review

Details

Original languageEnglish
Pages (from-to)98929-98945
Number of pages17
JournalIEEE Access
Volume8
DOIs
Publication statusPublished - 2020
Publication typeA1 Journal article-refereed

Abstract

Computer networks are in the Software Defined Networking (SDN) and Network Function Virtualization (NFV) era. SDN brings a whole new set of flexibility and possibilities into the network. The data plane of forwarding devices can be programmed to provide functionality for any protocol, and to perform novel network testing, diagnostics, and troubleshooting. One of the most dominant hardware architectures for implementing the programmable data plane is the Reconfigurable Match Tables (RMT) architecture. RMT's innovative programmable architecture enables support of novel networking protocols. However, there are certain shortcomings associated with its architecture that limit its scalability and lead to an unnecessarily complex architecture. In this paper, we present the details of an alternative packet parser and Match-Action pipeline. The parser sustains tenfold throughput at an area increase of only 32 percent. The pipeline supports unlimited combination of tables at minimum possible cost and provides a new level of flexibility to programmable Match-Action packet processing by allowing custom depth for actions. In addition, it has more advanced field-referencing mechanisms. Despite these architectural enhancements, it has 31 percent less area compared to RMT architecture.

ASJC Scopus subject areas

Keywords

  • Low-area hardware, Programmable data plane, Programmable packet processing, Software defined networking

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