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Hardware Architectures for the Fast Fourier Transform

Research output: Chapter in Book/Report/Conference proceedingChapterScientificpeer-review

Details

Original languageEnglish
Title of host publicationHandbook of Signal Processing Systems
PublisherSpringer
Pages613-647
ISBN (Electronic)978-3-319-91734-4
ISBN (Print)978-3-319-91733-7
DOIs
Publication statusPublished - 2019
Publication typeA3 Part of a book or another research book

Abstract

The fast Fourier transform (FFT) is a widely used algorithm in signal processing applications. FFT hardware architectures are designed to meet the requirements of the most demanding applications terms of performance, circuit area and/or power consumption. This chapter summarizes the research on FFT hardware architectures by presenting the FFT algorithms, the building blocks in FFT hardware architectures, the architectures themselves and the bit reversal algorithm.

Publication forum classification

Field of science, Statistics Finland