High-level synthesized 2-D IDCT/IDST implementation for HEVC codecs on FPGA
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
Details
Original language | English |
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Title of host publication | Proceedings of 2017 IEEE International Symposium on Circuits and Systems |
Publisher | IEEE |
Pages | 1-4 |
ISBN (Electronic) | 978-1-4673-6853-7 |
DOIs | |
Publication status | Published - 2017 |
Publication type | A4 Article in a conference publication |
Event | IEEE International Symposium on Circuits and Systems - Duration: 1 Jan 1900 → … |
Publication series
Name | |
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ISSN (Electronic) | 2379-447X |
Conference
Conference | IEEE International Symposium on Circuits and Systems |
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Period | 1/01/00 → … |
Abstract
This paper presents efficient inverse discrete cosine transform (IDCT) and inverse discrete sine transform (IDST) implementations for High Efficiency Video Coding (HEVC). The proposal makes use of high-level synthesis (HLS) to implement a complete HEVC 2-D IDCT/IDST architecture directly from the C code of a well-known Even-Odd decomposition algorithm. The final architecture includes a 4-point IDCT/IDST unit for the smallest transform blocks (TB), an 8/16/32-point IDCT unit for the other TBs, and a transpose memory for intermediate results. On Arria II FPGA, it supports real-time (60 fps) HEVC decoding of up to 2160p format with 12.4 kALUTs and 344 DSP blocks. Compared with the other existing HLS approach, the proposed solution is almost 5 times faster and is able to utilize available FPGA resources better.
Publication forum classification
Field of science, Statistics Finland
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