Impact of software bypassing on instruction level parallelism and register file traffic
Research output: Contribution to journal › Article › Scientific › peer-review
|Translated title of the contribution||Impact of software bypassing on instruction level parallelism and register file traffic|
|Journal||Lecture Notes in Computer Science|
|Publication status||Published - 2008|
|Publication type||A1 Journal article-refereed|
Software bypassing is a technique that allows programmer-controlled direct transfer of results of computations to the operands of data dependent operations, possibly removing the need to store some values in general purpose registers, while reducing the number of reads from the register file. Software bypassing also improves instruction level parallelism by reducing the number of false dependencies between operations caused by the reuse of registers. In this work we show how software bypassing affects cycle count and reduces register file reads and writes. We analyze previous register file bypassing methods and compare them with our improved software bypassing implementation. In addition, we propose heuristics when not to apply software bypassing to retain scheduling freedom when selecting function units for operations. The results show that we get at best 27% improvement to cycle count, as well as up to 48% less register reads and 45% less register writes with the use of bypassing.