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Improving logic-to-memory ratio in an embedded Multi-Processor system via code compression

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

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Improving logic-to-memory ratio in an embedded Multi-Processor system via code compression. / Airoldi, Roberto; Saastamoinen, Piia; Nurmi, Jari.

2012 International Symposium on System-on-Chip, SoC 2012, Tampere, Finland, 10-12 October, 2012. Piscataway, NJ : Institute of Electrical and Electronics Engineers IEEE, 2012. p. 1-4 13172275 (International Symposium on System-on-Chip).

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Harvard

Airoldi, R, Saastamoinen, P & Nurmi, J 2012, Improving logic-to-memory ratio in an embedded Multi-Processor system via code compression. in 2012 International Symposium on System-on-Chip, SoC 2012, Tampere, Finland, 10-12 October, 2012., 13172275, International Symposium on System-on-Chip, Institute of Electrical and Electronics Engineers IEEE, Piscataway, NJ, pp. 1-4. https://doi.org/10.1109/ISSoC.2012.6376371

APA

Airoldi, R., Saastamoinen, P., & Nurmi, J. (2012). Improving logic-to-memory ratio in an embedded Multi-Processor system via code compression. In 2012 International Symposium on System-on-Chip, SoC 2012, Tampere, Finland, 10-12 October, 2012 (pp. 1-4). [13172275] (International Symposium on System-on-Chip). Piscataway, NJ: Institute of Electrical and Electronics Engineers IEEE. https://doi.org/10.1109/ISSoC.2012.6376371

Vancouver

Airoldi R, Saastamoinen P, Nurmi J. Improving logic-to-memory ratio in an embedded Multi-Processor system via code compression. In 2012 International Symposium on System-on-Chip, SoC 2012, Tampere, Finland, 10-12 October, 2012. Piscataway, NJ: Institute of Electrical and Electronics Engineers IEEE. 2012. p. 1-4. 13172275. (International Symposium on System-on-Chip). https://doi.org/10.1109/ISSoC.2012.6376371

Author

Airoldi, Roberto ; Saastamoinen, Piia ; Nurmi, Jari. / Improving logic-to-memory ratio in an embedded Multi-Processor system via code compression. 2012 International Symposium on System-on-Chip, SoC 2012, Tampere, Finland, 10-12 October, 2012. Piscataway, NJ : Institute of Electrical and Electronics Engineers IEEE, 2012. pp. 1-4 (International Symposium on System-on-Chip).

Bibtex - Download

@inproceedings{1fef2ad1da6e4e778879fabb2a617e65,
title = "Improving logic-to-memory ratio in an embedded Multi-Processor system via code compression",
author = "Roberto Airoldi and Piia Saastamoinen and Jari Nurmi",
note = "Ei UT-numeroa 13.8.2013<br/>Contribution: organisation=tkt,FACT1=1<br/>Publisher name: Institute of Electrical and Electronics Engineers IEEE",
year = "2012",
doi = "10.1109/ISSoC.2012.6376371",
language = "English",
isbn = "978-1-4673-2895-1",
series = "International Symposium on System-on-Chip",
publisher = "Institute of Electrical and Electronics Engineers IEEE",
pages = "1--4",
booktitle = "2012 International Symposium on System-on-Chip, SoC 2012, Tampere, Finland, 10-12 October, 2012",

}

RIS (suitable for import to EndNote) - Download

TY - GEN

T1 - Improving logic-to-memory ratio in an embedded Multi-Processor system via code compression

AU - Airoldi, Roberto

AU - Saastamoinen, Piia

AU - Nurmi, Jari

N1 - Ei UT-numeroa 13.8.2013<br/>Contribution: organisation=tkt,FACT1=1<br/>Publisher name: Institute of Electrical and Electronics Engineers IEEE

PY - 2012

Y1 - 2012

U2 - 10.1109/ISSoC.2012.6376371

DO - 10.1109/ISSoC.2012.6376371

M3 - Conference contribution

SN - 978-1-4673-2895-1

T3 - International Symposium on System-on-Chip

SP - 1

EP - 4

BT - 2012 International Symposium on System-on-Chip, SoC 2012, Tampere, Finland, 10-12 October, 2012

PB - Institute of Electrical and Electronics Engineers IEEE

CY - Piscataway, NJ

ER -