Inexpensive Correctly Rounded Floating-Point Division and Square Root With Input Scaling

Research output: Scientific - peer-review › Conference contribution

Details

Original language	English
Title of host publication	2013 IEEE Workshop on Signal Processing Systems in Taipei, Taiwan, October 16th-18th, SIPS 2013
Publisher	Institute of Electrical and Electronics Engineers IEEE
Pages	159-164
Number of pages	6
ISBN (Print)	978-1-4673-6238-2
State	Published - 2013
Publication type	A4 Article in a conference publication
Event	IEEE Workshop on Signal Processing Systems -

Publication series

Name	IEEE Workshop on Signal Processing Systems
ISSN (Print)	2162-3562

Conference

Conference	IEEE Workshop on Signal Processing Systems
Period	1/01/00 → …

Abstract

Recent embedded DSPs are incorporating IEEE-compliant floating point arithmetic to ease the development of, e.g., multiple antenna MIMO in software-defined radio. An obvious choice of FPU architecture in DSP is to include a fused multiply-add (FMA) operation, which accelerates most DSP applications. Another advantage of FMA is that it enables fast software algorithms for, e.g., division and square root without much additional hardware. However, these algorithms are nontrivial to perform at the target accuracy to get the correctly rounded result without danger of overflow. Previous FMA-based systems either rely on a powerhungry wide intermediate format or forego correct rounding. A wide format is unattractive in a power-sensitive embedded environment since it requires enlarged register files, wider data buses and possibly a larger multiplier. We present provably correct algorithms for efficient IEEE-compliant division and square root with only a 32-bit format using hardware prescaling and postscaling steps. The required hardware has approximately 8% of area and power footprint of a single FMA unit.

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