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Integration Issues of a run-Time Configurable Memory Management Unit to a RISC Processor on FPGA

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Integration Issues of a run-Time Configurable Memory Management Unit to a RISC Processor on FPGA. / Shamani, Farid; Fakour Sevom, Vida; Ahonen, Tapani; Nurmi, Jari.

In: Microprocessors and Microsystems, Vol. 49, 03.2017, p. 179-191.

Research output: Contribution to journalArticleScientificpeer-review

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Shamani, F, Fakour Sevom, V, Ahonen, T & Nurmi, J 2017, 'Integration Issues of a run-Time Configurable Memory Management Unit to a RISC Processor on FPGA', Microprocessors and Microsystems, vol. 49, pp. 179-191. https://doi.org/10.1016/j.micpro.2016.12.001

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Shamani, Farid ; Fakour Sevom, Vida ; Ahonen, Tapani ; Nurmi, Jari. / Integration Issues of a run-Time Configurable Memory Management Unit to a RISC Processor on FPGA. In: Microprocessors and Microsystems. 2017 ; Vol. 49. pp. 179-191.

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@article{6dba1901c338461d9d1c2e741bdbd8c6,
title = "Integration Issues of a run-Time Configurable Memory Management Unit to a RISC Processor on FPGA",
abstract = "This paper presents the integration issues of a proposed run-time configurable Memory Management Unit (MMU) to the COFFEE processor developed by our group at Tampere University of Technology. The MMU consists of three Translation Lookaside Buffers (TLBs) in two levels of hierarchy. The MMU and its respective integration to the processor is prototyped on a Field Programmable Gate Array (FPGA) device. Furthermore, analytical results of scaling the second-level Unified TLB (UTLB) to three configurations (with 16, 32, and 64 entries) with respect to the effect on overall hit rate as well as the energy consumption are shown. The critical path analysis of the logical design running on the target FPGA is presented together with a description of optimization techniques to improve static timing performance which leads to gain 22.75{\%} speed-up. We could reach to our target operating frequency of 200 MHz for the 64-entry UTLB and, thus, it is our preferred option. The 32-entry UTLB configuration provides a decent trade-off for resource-constrained or speed-critical hardware designs while the 16-entry configuration poses unsatisfactory performance. Next, integration challenges and how to resolve each of them (such as employing a wrapper around the MMU, modifying the hardware description of the COFFEE core, etc.) are investigated in detail. This paper not only provides invaluable information with regard to the implementation and integration phases of the MMU to a RISC processor, it opens a new horizon to our processor to provide virtual memory for its running operating system without degrading the operating frequency. This work also tends toward being a general reference for future integration to the COFFEE core as well as other similar processor architectures.",
keywords = "FPGA Implementation, Memory Management Unit, Virtual-to-Physical Address Translation, Run-Time Configurable MMU, COFFEE RISC Processor",
author = "Farid Shamani and {Fakour Sevom}, Vida and Tapani Ahonen and Jari Nurmi",
year = "2017",
month = "3",
doi = "10.1016/j.micpro.2016.12.001",
language = "English",
volume = "49",
pages = "179--191",
journal = "Microprocessors and Microsystems",
issn = "0141-9331",
publisher = "Elsevier",

}

RIS (suitable for import to EndNote) - Download

TY - JOUR

T1 - Integration Issues of a run-Time Configurable Memory Management Unit to a RISC Processor on FPGA

AU - Shamani, Farid

AU - Fakour Sevom, Vida

AU - Ahonen, Tapani

AU - Nurmi, Jari

PY - 2017/3

Y1 - 2017/3

N2 - This paper presents the integration issues of a proposed run-time configurable Memory Management Unit (MMU) to the COFFEE processor developed by our group at Tampere University of Technology. The MMU consists of three Translation Lookaside Buffers (TLBs) in two levels of hierarchy. The MMU and its respective integration to the processor is prototyped on a Field Programmable Gate Array (FPGA) device. Furthermore, analytical results of scaling the second-level Unified TLB (UTLB) to three configurations (with 16, 32, and 64 entries) with respect to the effect on overall hit rate as well as the energy consumption are shown. The critical path analysis of the logical design running on the target FPGA is presented together with a description of optimization techniques to improve static timing performance which leads to gain 22.75% speed-up. We could reach to our target operating frequency of 200 MHz for the 64-entry UTLB and, thus, it is our preferred option. The 32-entry UTLB configuration provides a decent trade-off for resource-constrained or speed-critical hardware designs while the 16-entry configuration poses unsatisfactory performance. Next, integration challenges and how to resolve each of them (such as employing a wrapper around the MMU, modifying the hardware description of the COFFEE core, etc.) are investigated in detail. This paper not only provides invaluable information with regard to the implementation and integration phases of the MMU to a RISC processor, it opens a new horizon to our processor to provide virtual memory for its running operating system without degrading the operating frequency. This work also tends toward being a general reference for future integration to the COFFEE core as well as other similar processor architectures.

AB - This paper presents the integration issues of a proposed run-time configurable Memory Management Unit (MMU) to the COFFEE processor developed by our group at Tampere University of Technology. The MMU consists of three Translation Lookaside Buffers (TLBs) in two levels of hierarchy. The MMU and its respective integration to the processor is prototyped on a Field Programmable Gate Array (FPGA) device. Furthermore, analytical results of scaling the second-level Unified TLB (UTLB) to three configurations (with 16, 32, and 64 entries) with respect to the effect on overall hit rate as well as the energy consumption are shown. The critical path analysis of the logical design running on the target FPGA is presented together with a description of optimization techniques to improve static timing performance which leads to gain 22.75% speed-up. We could reach to our target operating frequency of 200 MHz for the 64-entry UTLB and, thus, it is our preferred option. The 32-entry UTLB configuration provides a decent trade-off for resource-constrained or speed-critical hardware designs while the 16-entry configuration poses unsatisfactory performance. Next, integration challenges and how to resolve each of them (such as employing a wrapper around the MMU, modifying the hardware description of the COFFEE core, etc.) are investigated in detail. This paper not only provides invaluable information with regard to the implementation and integration phases of the MMU to a RISC processor, it opens a new horizon to our processor to provide virtual memory for its running operating system without degrading the operating frequency. This work also tends toward being a general reference for future integration to the COFFEE core as well as other similar processor architectures.

KW - FPGA Implementation

KW - Memory Management Unit

KW - Virtual-to-Physical Address Translation

KW - Run-Time Configurable MMU

KW - COFFEE RISC Processor

U2 - 10.1016/j.micpro.2016.12.001

DO - 10.1016/j.micpro.2016.12.001

M3 - Article

VL - 49

SP - 179

EP - 191

JO - Microprocessors and Microsystems

JF - Microprocessors and Microsystems

SN - 0141-9331

ER -