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Low-latency Packet Parsing in Software Defined Networks

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Details

Original languageEnglish
Title of host publication2018 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)
PublisherIEEE
ISBN (Electronic)978-1-5386-7656-1
DOIs
Publication statusPublished - 13 Dec 2018
Publication typeA4 Article in a conference publication
EventIEEE Nordic Circuits and Systems Conference - Tallinn, Estonia
Duration: 30 Oct 201831 Oct 2018

Conference

ConferenceIEEE Nordic Circuits and Systems Conference
Abbreviated titleNorCAS 2018
CountryEstonia
CityTallinn
Period30/10/1831/10/18

Abstract

Packet parsing is the first step in processing of packets in devices such as switches and routers. In this paper, we present a totally new program control unit as well as further enhancements for a recently designed packet parser architecture which can parse headers of most commonly used protocols such as Ethernet, IPv4, IPv6 and TCP in a time window shorter than 10 nanoseconds. However, when it comes to parsing variable-length headers and multiple stacked headers, it deviates from its maximum throughput due to inefficiencies in its program control logic. We have designed and employed a more advanced program control logic that improves parsing time of variable length headers such as IPv4 header by up to 48 percent and parsing time of typical header stacks used on the Internet by 16 to 21.42 percent. Our solution can sustain aggregate throughput of 640 Gbps while requiring only 30 percent of the number of gates used in the parser used in the Reconfigurable Match Tables architecture.