Low-Power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
Details
| Original language | English |
|---|---|
| Title of host publication | 2019 IEEE International Conference on Acoustics, Speech and Signal Processing Proceedings |
| Publisher | IEEE |
| ISBN (Electronic) | 978-1-4799-8131-1 |
| DOIs | |
| Publication status | Published - 17 Apr 2019 |
| Publication type | A4 Article in a conference publication |
| Event | IEEE International Conference on Acoustics, Speech and Signal Processing - Brighton, United Kingdom Duration: 12 May 2019 → 17 May 2019 |
Conference
| Conference | IEEE International Conference on Acoustics, Speech and Signal Processing |
|---|---|
| Country | United Kingdom |
| City | Brighton |
| Period | 12/05/19 → 17/05/19 |
Abstract
This paper describes a low-power processor tailored for fast Fourier transform computations where transport triggering template is exploited. The processor is software-programmable while retaining an energy-efficiency comparable to existing fixed-function implementations. The power savings are achieved by compressing the computation kernel into one instruction word. The word is stored in an instruction loop buffer, which is more power-efficient than regular instruction memory storage. The processor supports all power-of-two FFT sizes from 64 to 16384 and given 1 mJ of energy, it can compute 20916 transforms of size 1024.
Keywords
- Fast Fourier transform, Transport triggered architecture, Application-Specific Instruction-Set Processor