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Low-Power Programmable Processor for Fast Fourier Transform Based on Transport Triggered Architecture

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Details

Original languageEnglish
Title of host publication2019 IEEE International Conference on Acoustics, Speech and Signal Processing Proceedings
PublisherIEEE
ISBN (Electronic)978-1-4799-8131-1
DOIs
Publication statusPublished - 17 Apr 2019
Publication typeA4 Article in a conference publication
EventIEEE International Conference on Acoustics, Speech and Signal Processing - Brighton, United Kingdom
Duration: 12 May 201917 May 2019

Conference

ConferenceIEEE International Conference on Acoustics, Speech and Signal Processing
CountryUnited Kingdom
CityBrighton
Period12/05/1917/05/19

Abstract

This paper describes a low-power processor tailored for fast Fourier transform computations where transport triggering template is exploited. The processor is software-programmable while retaining an energy-efficiency comparable to existing fixed-function implementations. The power savings are achieved by compressing the computation kernel into one instruction word. The word is stored in an instruction loop buffer, which is more power-efficient than regular instruction memory storage. The processor supports all power-of-two FFT sizes from 64 to 16384 and given 1 mJ of energy, it can compute 20916 transforms of size 1024.

Keywords

  • Fast Fourier transform, Transport triggered architecture, Application-Specific Instruction-Set Processor

Publication forum classification

Field of science, Statistics Finland