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Mapping parameterized cyclo-static dataflow graphs onto configurable hardware

Research output: Contribution to journalArticleScientificpeer-review

Details

Original languageEnglish
Pages (from-to)285-301
Number of pages17
JournalJournal of Signal Processing Systems
Volume66
Issue number3
DOIs
Publication statusPublished - 2012
Publication typeA1 Journal article-refereed

Abstract

In recent years, parameterized dataflow has evolved as a useful framework for modeling synchronous and cyclo-static graphs in which arbitrary parameters can be changed dynamically. Parameterized dataflow has proven to have significant expressive power for managing dynamics of DSP applications in important ways. However, efficient hardware synthesis techniques for parameterized dataflow representations are lacking. This paper addresses this void; specifically, the paper investigates efficient field programmable gate array (FPGA)-based implementation of parameterized cyclo-static dataflow (PCSDF) graphs. We develop a scheduling technique for throughput-constrained minimization of dataflow buffering requirements when mapping PCSDF representations of DSP applications onto FPGAs. The proposed scheduling technique is integrated with an existing formal schedule model, called the generalized schedule tree, to reduce schedule cost. To demonstrate our new, hardware-oriented PCSDF scheduling technique, we have designed a real-time base station emulator prototype based on a subset of long-term evolution (LTE), which is a key cellular standard.

Keywords

  • 4G communication systems, Dataflow modeling, FPGA implementation, Parameterized dataflow, Scheduling