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Mapping parameterized cyclo-static dataflow graphs onto configurable hardware

Research output: Contribution to journalArticleScientificpeer-review

Standard

Mapping parameterized cyclo-static dataflow graphs onto configurable hardware. / Kee, Hojin; Shen, Chung Ching; Bhattacharyya, Shuvra S.; Wong, Ian; Rao, Yong; Kornerup, Jacob.

In: Journal of Signal Processing Systems, Vol. 66, No. 3, 2012, p. 285-301.

Research output: Contribution to journalArticleScientificpeer-review

Harvard

Kee, H, Shen, CC, Bhattacharyya, SS, Wong, I, Rao, Y & Kornerup, J 2012, 'Mapping parameterized cyclo-static dataflow graphs onto configurable hardware', Journal of Signal Processing Systems, vol. 66, no. 3, pp. 285-301. https://doi.org/10.1007/s11265-011-0599-5

APA

Kee, H., Shen, C. C., Bhattacharyya, S. S., Wong, I., Rao, Y., & Kornerup, J. (2012). Mapping parameterized cyclo-static dataflow graphs onto configurable hardware. Journal of Signal Processing Systems, 66(3), 285-301. https://doi.org/10.1007/s11265-011-0599-5

Vancouver

Kee H, Shen CC, Bhattacharyya SS, Wong I, Rao Y, Kornerup J. Mapping parameterized cyclo-static dataflow graphs onto configurable hardware. Journal of Signal Processing Systems. 2012;66(3):285-301. https://doi.org/10.1007/s11265-011-0599-5

Author

Kee, Hojin ; Shen, Chung Ching ; Bhattacharyya, Shuvra S. ; Wong, Ian ; Rao, Yong ; Kornerup, Jacob. / Mapping parameterized cyclo-static dataflow graphs onto configurable hardware. In: Journal of Signal Processing Systems. 2012 ; Vol. 66, No. 3. pp. 285-301.

Bibtex - Download

@article{33d87770f4f349a686be8327698293cc,
title = "Mapping parameterized cyclo-static dataflow graphs onto configurable hardware",
abstract = "In recent years, parameterized dataflow has evolved as a useful framework for modeling synchronous and cyclo-static graphs in which arbitrary parameters can be changed dynamically. Parameterized dataflow has proven to have significant expressive power for managing dynamics of DSP applications in important ways. However, efficient hardware synthesis techniques for parameterized dataflow representations are lacking. This paper addresses this void; specifically, the paper investigates efficient field programmable gate array (FPGA)-based implementation of parameterized cyclo-static dataflow (PCSDF) graphs. We develop a scheduling technique for throughput-constrained minimization of dataflow buffering requirements when mapping PCSDF representations of DSP applications onto FPGAs. The proposed scheduling technique is integrated with an existing formal schedule model, called the generalized schedule tree, to reduce schedule cost. To demonstrate our new, hardware-oriented PCSDF scheduling technique, we have designed a real-time base station emulator prototype based on a subset of long-term evolution (LTE), which is a key cellular standard.",
keywords = "4G communication systems, Dataflow modeling, FPGA implementation, Parameterized dataflow, Scheduling",
author = "Hojin Kee and Shen, {Chung Ching} and Bhattacharyya, {Shuvra S.} and Ian Wong and Yong Rao and Jacob Kornerup",
year = "2012",
doi = "10.1007/s11265-011-0599-5",
language = "English",
volume = "66",
pages = "285--301",
journal = "Journal of Signal Processing Systems",
issn = "1939-8018",
publisher = "Springer Verlag",
number = "3",

}

RIS (suitable for import to EndNote) - Download

TY - JOUR

T1 - Mapping parameterized cyclo-static dataflow graphs onto configurable hardware

AU - Kee, Hojin

AU - Shen, Chung Ching

AU - Bhattacharyya, Shuvra S.

AU - Wong, Ian

AU - Rao, Yong

AU - Kornerup, Jacob

PY - 2012

Y1 - 2012

N2 - In recent years, parameterized dataflow has evolved as a useful framework for modeling synchronous and cyclo-static graphs in which arbitrary parameters can be changed dynamically. Parameterized dataflow has proven to have significant expressive power for managing dynamics of DSP applications in important ways. However, efficient hardware synthesis techniques for parameterized dataflow representations are lacking. This paper addresses this void; specifically, the paper investigates efficient field programmable gate array (FPGA)-based implementation of parameterized cyclo-static dataflow (PCSDF) graphs. We develop a scheduling technique for throughput-constrained minimization of dataflow buffering requirements when mapping PCSDF representations of DSP applications onto FPGAs. The proposed scheduling technique is integrated with an existing formal schedule model, called the generalized schedule tree, to reduce schedule cost. To demonstrate our new, hardware-oriented PCSDF scheduling technique, we have designed a real-time base station emulator prototype based on a subset of long-term evolution (LTE), which is a key cellular standard.

AB - In recent years, parameterized dataflow has evolved as a useful framework for modeling synchronous and cyclo-static graphs in which arbitrary parameters can be changed dynamically. Parameterized dataflow has proven to have significant expressive power for managing dynamics of DSP applications in important ways. However, efficient hardware synthesis techniques for parameterized dataflow representations are lacking. This paper addresses this void; specifically, the paper investigates efficient field programmable gate array (FPGA)-based implementation of parameterized cyclo-static dataflow (PCSDF) graphs. We develop a scheduling technique for throughput-constrained minimization of dataflow buffering requirements when mapping PCSDF representations of DSP applications onto FPGAs. The proposed scheduling technique is integrated with an existing formal schedule model, called the generalized schedule tree, to reduce schedule cost. To demonstrate our new, hardware-oriented PCSDF scheduling technique, we have designed a real-time base station emulator prototype based on a subset of long-term evolution (LTE), which is a key cellular standard.

KW - 4G communication systems

KW - Dataflow modeling

KW - FPGA implementation

KW - Parameterized dataflow

KW - Scheduling

UR - http://www.scopus.com/inward/record.url?scp=84888881360&partnerID=8YFLogxK

U2 - 10.1007/s11265-011-0599-5

DO - 10.1007/s11265-011-0599-5

M3 - Article

VL - 66

SP - 285

EP - 301

JO - Journal of Signal Processing Systems

JF - Journal of Signal Processing Systems

SN - 1939-8018

IS - 3

ER -