Multilevel outphasing power amplifier system with a transmission-line power combiner
Research output: Chapter in Book/Report/Conference proceeding › Conference contribution › Scientific › peer-review
Details
| Original language | English |
|---|---|
| Title of host publication | Conference on Ph.D. Research in Microelectronics and Electronics (PRIME 2016) |
| Publisher | IEEE |
| Number of pages | 4 |
| ISBN (Electronic) | 978-1-5090-0493-5 |
| DOIs | |
| Publication status | Published - Jun 2016 |
| Publication type | A4 Article in a conference publication |
| Event | Conference on Ph. D. Research in Microelectronics and Electronics - Duration: 1 Jan 1900 → … |
Conference
| Conference | Conference on Ph. D. Research in Microelectronics and Electronics |
|---|---|
| Period | 1/01/00 → … |
Abstract
This paper presents a multilevel outphasing power amplifier (PA) system consisting of eight class-D unit PAs on 28 nm CMOS and an off-chip transmission-line power combiner. The combiner, implemented on PCB with microstrip lines, was designed to operate at 1.8 GHz frequency and filter out the third and fifth harmonics generated by the PAs. The combiner layout was designed so that the line spacing increases towards the output to reduce coupling, while the lines are equal in length. The simulated maximum output power is 32.3 dBm (1.71 W) with an efficiency of 34.4%. With 20 MHz and 100 MHz LTE signals, average efficiencies of 15.2% and 15.1% were achieved, respectively.