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Multiplier-Free Decimators with Efficient VLSI Implementation for Sigma-Delta A/D Converters

Research output: Chapter in Book/Report/Conference proceedingConference contributionScientificpeer-review

Details

Original languageEnglish
Title of host publicationPresented in IEEE Workshop on VLSI Signal Processing (Monterey, CA), Nov. 1988; included in VLSI Signal Processing 3, edited by R.W. Brodersen and H.S.Moscovitz
Place of PublicationNew York
PublisherIEEE Press
Pages523-534
Publication statusPublished - 1988
Publication typeA4 Article in a conference publication

Publication forum classification