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Multiplierless Unity-Gain SDF FFTs

Research output: Contribution to journalArticleScientificpeer-review


Original languageEnglish
Pages (from-to)3003-3007
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number9
Early online date2016
Publication statusPublished - Sep 2016
Publication typeA1 Journal article-refereed


In this brief, we propose a novel approach to implement multiplierless unity-gain single-delay feedback fast Fourier transforms (FFTs). Previous methods achieve unity-gain FFTs by using either complex multipliers or nonunity-gain rotators with additional scaling compensation. Conversely, this brief proposes unity-gain FFTs without compensation circuits, even when using nonunity-gain rotators. This is achieved by a joint design of rotators, so that the entire FFT is scaled by a power of two, which is then shifted to unity. This reduces the amount of hardware resources of the FFT architecture, while having high accuracy in the calculations. The proposed approach can be applied to any FFT size, and various designs for different FFT sizes are presented.

Publication forum classification

Field of science, Statistics Finland