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Multiprocessor scheduling of dataflow programs within the reconfigurable video coding framework

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Original languageEnglish
Title of host publicationAlgorithm-Architecture Matching for Signal and Image Processing - Best Papers from Design and Architectures for Signal and Image Processing 2007 and 2008 and 2009
Number of pages15
Volume73 LNEE
Publication statusPublished - 2011
Publication typeA4 Article in a conference publication

Publication series

NameLecture Notes in Electrical Engineering
Volume73 LNEE
ISSN (Print)18761100
ISSN (Electronic)18761119


The new Reconfigurable Video Coding (RVC) standard of MPEG marks a transition in the way video coding algorithms are specified. Imperative and monolithic reference software is replaced by a collection of interconnected, concurrent functional units (FUs) that are specified with the actor-oriented CAL language. Different connections between the FUs lead to different decoders: all previous standards (MPEG-2 MP, MPEG-4 SP, AVC, SVC, ⋯) can be built with RVC FUs. The RVC standard does not specify a schedule or scheduling heuristic for running the decoder implementations consisting of FUs. Previous work has shown a way to produce efficient quasi-static schedules for CAL actor networks. This paper discusses the mapping of RVC FUs to multiprocessor systems, utilizing quasi-static scheduling. A design space exploration tool has been developed, that maps the FUs to a multiprocessor system in order to maximize the decoder throughput. Depending on the inter-processor communication cost, the tool points out different mappings of FUs to processing elements.