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Multithreaded simulation for synchronous dataflow graphs

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Multithreaded simulation for synchronous dataflow graphs. / Hsu, Chia Jui; Pino, José Luis; Bhattacharyya, Shuvra S.

In: ACM Transactions on Design Automation of Electronic Systems, Vol. 16, No. 3, 25, 06.2011.

Research output: Contribution to journalArticleScientificpeer-review

Harvard

Hsu, CJ, Pino, JL & Bhattacharyya, SS 2011, 'Multithreaded simulation for synchronous dataflow graphs', ACM Transactions on Design Automation of Electronic Systems, vol. 16, no. 3, 25. https://doi.org/10.1145/1970353.1970358

APA

Hsu, C. J., Pino, J. L., & Bhattacharyya, S. S. (2011). Multithreaded simulation for synchronous dataflow graphs. ACM Transactions on Design Automation of Electronic Systems, 16(3), [25]. https://doi.org/10.1145/1970353.1970358

Vancouver

Hsu CJ, Pino JL, Bhattacharyya SS. Multithreaded simulation for synchronous dataflow graphs. ACM Transactions on Design Automation of Electronic Systems. 2011 Jun;16(3). 25. https://doi.org/10.1145/1970353.1970358

Author

Hsu, Chia Jui ; Pino, José Luis ; Bhattacharyya, Shuvra S. / Multithreaded simulation for synchronous dataflow graphs. In: ACM Transactions on Design Automation of Electronic Systems. 2011 ; Vol. 16, No. 3.

Bibtex - Download

@article{daf7aff2ec704a6390ad28ca0f9f0010,
title = "Multithreaded simulation for synchronous dataflow graphs",
abstract = "For system simulation, Synchronous DataFlow (SDF) has been widely used as a core model of computation in design tools for digital communication and signal processing systems. The traditional approach for simulating SDF graphs is to compute and execute static schedules in single-processor desktop environments. Nowadays, however, multicore processors are increasingly popular desktop platforms for their potential performance improvements through thread-level parallelism. Without novel scheduling and simulation techniques that explicitly explore thread-level parallelism for executing SDF graphs, current design tools gain only minimal performance improvements on multicore platforms. In this article, we present a new multithreaded simulation scheduler, called MSS, to provide simulation runtime speedup for executing SDF graphs on multicore processors. MSS strategically integrates graph clustering, intracluster scheduling, actor vectorization, and intercluster buffering techniques to construct InterThread Communication (ITC) graphs at compile-time. MSS then applies efficient synchronization and dynamic scheduling techniques at runtime for executing ITC graphs in multithreaded environments. We have implemented MSS in the Advanced Design System (ADS) from Agilent Technologies. On an Intel dual-core, hyper-threading (4 processing units) processor, our results from this implementation demonstrate up to 3.5 times speedup in simulating modern wireless communication systems (e.g., WCDMA3G, CDMA 2000, WiMax, EDGE, and Digital TV).",
keywords = "Multithreaded simulation, Scheduling, Synchronous dataflow",
author = "Hsu, {Chia Jui} and Pino, {Jos{\'e} Luis} and Bhattacharyya, {Shuvra S.}",
year = "2011",
month = "6",
doi = "10.1145/1970353.1970358",
language = "English",
volume = "16",
journal = "ACM Transactions on Design Automation of Electronic Systems",
issn = "1084-4309",
publisher = "Association for Computing Machinery",
number = "3",

}

RIS (suitable for import to EndNote) - Download

TY - JOUR

T1 - Multithreaded simulation for synchronous dataflow graphs

AU - Hsu, Chia Jui

AU - Pino, José Luis

AU - Bhattacharyya, Shuvra S.

PY - 2011/6

Y1 - 2011/6

N2 - For system simulation, Synchronous DataFlow (SDF) has been widely used as a core model of computation in design tools for digital communication and signal processing systems. The traditional approach for simulating SDF graphs is to compute and execute static schedules in single-processor desktop environments. Nowadays, however, multicore processors are increasingly popular desktop platforms for their potential performance improvements through thread-level parallelism. Without novel scheduling and simulation techniques that explicitly explore thread-level parallelism for executing SDF graphs, current design tools gain only minimal performance improvements on multicore platforms. In this article, we present a new multithreaded simulation scheduler, called MSS, to provide simulation runtime speedup for executing SDF graphs on multicore processors. MSS strategically integrates graph clustering, intracluster scheduling, actor vectorization, and intercluster buffering techniques to construct InterThread Communication (ITC) graphs at compile-time. MSS then applies efficient synchronization and dynamic scheduling techniques at runtime for executing ITC graphs in multithreaded environments. We have implemented MSS in the Advanced Design System (ADS) from Agilent Technologies. On an Intel dual-core, hyper-threading (4 processing units) processor, our results from this implementation demonstrate up to 3.5 times speedup in simulating modern wireless communication systems (e.g., WCDMA3G, CDMA 2000, WiMax, EDGE, and Digital TV).

AB - For system simulation, Synchronous DataFlow (SDF) has been widely used as a core model of computation in design tools for digital communication and signal processing systems. The traditional approach for simulating SDF graphs is to compute and execute static schedules in single-processor desktop environments. Nowadays, however, multicore processors are increasingly popular desktop platforms for their potential performance improvements through thread-level parallelism. Without novel scheduling and simulation techniques that explicitly explore thread-level parallelism for executing SDF graphs, current design tools gain only minimal performance improvements on multicore platforms. In this article, we present a new multithreaded simulation scheduler, called MSS, to provide simulation runtime speedup for executing SDF graphs on multicore processors. MSS strategically integrates graph clustering, intracluster scheduling, actor vectorization, and intercluster buffering techniques to construct InterThread Communication (ITC) graphs at compile-time. MSS then applies efficient synchronization and dynamic scheduling techniques at runtime for executing ITC graphs in multithreaded environments. We have implemented MSS in the Advanced Design System (ADS) from Agilent Technologies. On an Intel dual-core, hyper-threading (4 processing units) processor, our results from this implementation demonstrate up to 3.5 times speedup in simulating modern wireless communication systems (e.g., WCDMA3G, CDMA 2000, WiMax, EDGE, and Digital TV).

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KW - Scheduling

KW - Synchronous dataflow

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